• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.1
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• pp.107-112
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• 2009

This paper describes design and fabrication issues of the SiP(System in Package) one-chip for a portable digital broadcasting receiver. It includes RF tuner chip, demodulator chip and passive components for the receiver system. When we apply the SiP one-chip technology to the broadcasting receiver, the system board size can be reduced from $776mm^2$ to $144mm^2$. SiP one-chip has an advantage that the area reduces more 81% than separated chips. Also the sensitivity performance advances -1dBm about 36 channels in the RF weak electric field, the power consumption reduces about 2mW and the C/N keeps on the same level.

• JSTS:Journal of Semiconductor Technology and Science
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• v.5 no.4
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• pp.255-261
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• 2005

With the advent of sub-90nm technologies, the system-on-chip (SoC) and system-in-package (SiP) are becoming the trend in delivering low-cost, low-power, and small-form-factor consumer electronic systems running at multiple GHz. The shortened transistor channel length reduces the transistor switching cycles to the range of several picoseconds, yet the time-of-flights of the critical on-chip and off-chip interconnects are in the range of 10 picoseconds for 1.5mm-long wires and 100 picoseconds for 15mm-long wires. Designers realize the bottleneck today often lies at chip-to-chip interconnects and the industry needs a good model to compute the inductance in these parts of circuits. In this paper we propose a new method for extracting accurate equivalent inductance circuit models for SPICE-level circuit simulations of system-on-chip (SoC) and system-in-package (SiP) designs. In our method, geometrical meshes are created and numerical methods are used to find the solutions for the electromagnetic fields over the fine meshes. In this way, multiple-GHz SoC and SiP designers can use accurate inductance modeling and interconnect optimization to achieve high yields.

• Journal of information and communication convergence engineering
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• v.6 no.2
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• pp.122-128
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• 2008

Multiprocessor architectures and platforms, such as, a multiprocessor system on chip (MPSoC) recently introduced to extend the applicability of the Moore's law, depend upon concurrency and synchronization in both software and hardware to enhance design productivity and system performance. With the rapidly approaching billion transistors era, some of the main problem in deep sub-micron technologies characterized by gate lengths in the range of 60-90 nm will arise from non scalable wire delays, errors in signal integrity and non-synchronized communication. These problems may be addressed by the use of Network on Chip (NOC) architecture for future System-on-Chip (SoC). We have modeled a concurrent architecture for a customizable and scalable NOC in a system level modeling environment using MLDesigner (from MLD Inc.). Varying network loads under various traffic scenarios were applied to obtain realistic performance metrics. We provide the simulation results for latency as a function of the buffer size. We have abstracted the area results for NOC components from its FPGA implementation. Modeled NOC architecture supports three different levels of quality-of-service (QoS).

• Journal of the Korean Society for Precision Engineering
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• v.16 no.6
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• pp.133-140
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• 1999

In this study, a monitoring method to detect chip disposal state in drilling system based on neural network was proposed and its performance was evaluated. If chip flow is bad during drilling, not only the static component but also the fluctuation of dynamic component of drilling. Drilling torque is indirectly measured by sensing spindle motor power through a AC spindle motor drive system. Spindle motor power being measured drilling, four quantities such as variance/mean, mean absolute deviation, gradient, event count were calculated as feature vectors and then presented to the neural network to make a decision on chip disposal state. The selected features are sensitive to the change of chip disposal state but comparatively insensitive to the change of drilling condition. The 3 layerd neural network with error back propagation algorithm has been used. Experimental results show that the proposed monitoring system can successfully recognize the chip disposal state over a wide range of drilling condition even though it is trained under a certain drilling condition.

• ETRI Journal
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• v.27 no.5
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• pp.497-503
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• 2005

In this paper, we present a performance analysis for an MPEG-4 video codec based on the on-chip network communication architecture. The existing on-chip buses of system-on-a-chip (SoC) have some limitation on data traffic bandwidth since a large number of silicon IPs share the bus. An on-chip network is introduced to solve the problem of on-chip buses, in which the concept of a computer network is applied to the communication architecture of SoC. We compared the performance of the MPEG-4 video codec based on the on-chip network and Advanced Micro-controller Bus Architecture (AMBA) on-chip bus. Experimental results show that the performance of the MPEG-4 video codec based on the on-chip network is improved over 50% compared to the design based on a multi-layer AMBA bus.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.7
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• pp.641-648
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• 2002

The study on the chip waveform design to minimize multiple-access interference (MAI) and its performance evaluation are very important since chip waveform decides the signal quality and system capacity of the direct-sequence CDMA wireless communication system. This paper suggests the analytical chip waveform to minimize the MAI. The BER and throughput performances achieved by the proposed analytical optimum chip waveform are compared with those of the conventional chip waveforms in the Nakagami-m distribution frequency selective channel when the differential phase shift keying (DPSK) is employed in DS-CDMA system. From the numerical results, capacity and throughput are improved about 2 times and 1.4 times respectively when it is compared with the Kaiser chip waveform that is considered as one of the best in the conventional ones.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.53 no.3
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• pp.129-133
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• 2004

As In DS/CDMA(direct sequence code division multiple access) system, the system capacity is limited by multiple access interference(MAI), and self-interference(SI) resulting from the multi-path propagation of the desired user signal. This paper, which the approximated analytic chip waveforms are nearly the same as the computer generated chip waveforms are shown. And then, the BER(Bit Error Rate) performances in CDMA system using the approximated analytic chip waveforms are shown.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.2B no.4
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• pp.207-213
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• 2002

The paper introduces a switched reluctance motor drive system based on an 80C31 and an Intel 80C 196KB single-chip microprocessor control. Advance schemes are used in turn-on and turn-off angles with the power converter's main switches during traction and regenerative braking. The principles of traction speed control and braking torque control are given. The hardware and software patterns in the 80c31 and the Intel 80C196KB single-chip microprocessor control system are also presented.

• Journal of Sensor Science and Technology
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• v.20 no.3
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• pp.162-167
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• 2011

In this paper, we propose a vision system using a field programmable gate array(FPGA) and a smart vision chip. The output of the vision chip is varied by illumination conditions. This chip is suitable as a surveillance system in a dynamic environment. However, because the output swing of a smart vision chip is too small to definitely confirm the warning signal with the FPGA, a modification was needed for a reliable signal. The proposed system is based on a transmission control protocol/internet protocol(TCP/IP) that enables monitoring from a remote place. The warning signal indicates that some objects are too near.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.1
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• pp.1-8
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• 2015

To produce the white light, there are a single chip method using the blue light and phosphor coating, a multi chip method by mixing R, G, B light.. Multi chip method is proper for the smart lighting system by controling color and color temperature. And color rendering of single chip LED is good by even spectral distribution. To apply application technic like smart light system, this paper analyzed the properties of single chip LED and RGB multi chip LED, and implemented the 2 part subject evaluation for single chip LED and RGB multi chip LED. The first part is comparison of properties for single chip LED and RGB multi chip and second part is color appearance evaluation of 8 colors in each lighting environment.