• Journal of the Korean Institute of Gas
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• v.3 no.2 s.7
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• pp.62-69
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• 1999

This paper presents a design method of dynamic positioning control system(DPS) for floating Platform with rotatable and retractable thrusters using H$\infty$ servo control design method. The norm band of uncertainty is captured by multiplicative perturbation between nominal model and reduced order model. A controller robust to the uncertainty is designed applying H$\infty$ synthesis. The control law satisfying robust stability and nominal performance condition is determined through the mixed sensitivity approach. The control algorithm was evaluated on the basis of computer simulation for a proposed DPS design method and experiments was carried out with an image processing method for measurement of DPS position in a water tank The results of overall experiments show that proposed control method will be good to keep at a specified position. And they are compared with the experimental results by LQG synthesis and H$\infty$ optimal control design method.

• The Journal of the Acoustical Society of Korea
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• v.22 no.2
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• pp.135-144
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• 2003

A method for the automatic segmentation of speech signals is described. The method is dedicated to the construction of a large database for a Text-To-Speech (TTS) synthesis system. The main issue of the work involves the refinement of an initial estimation of phone boundaries which are provided by an alignment, based on a Hidden Market Model(HMM). Multi-layer perceptron (MLP) was used as a phone boundary detector. To increase the performance of segmentation, a technique which individually trains an MLP according to phonetic transition is proposed. The optimum partitioning of the entire phonetic transition space is constructed from the standpoint of minimizing the overall deviation from hand labelling positions. With single speaker stimuli, the experimental results showed that more than 95% of all phone boundaries have a boundary deviation from the reference position smaller than 20 ms, and the refinement of the boundaries reduces the root mean square error by about 25%.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.8
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• pp.45-52
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• 2017

This paper presents a high-performance software-hardware dehazing system based on a dedicated hardware accelerator for the haze removal. In the proposed system, the dedicated hardware accelerator performs the dark-channel-prior-based dehazing process, and the software performs the other control processes. For this purpose, the dehazing process is realized as an OpenCL kernel by finding the inherent parallelism in the algorithm and is synthesized into a hardware by employing a high-level-synthesis technique. The proposed system executes the dehazing process much faster than the previous software-only dehazing system: the performance improvement is up to 96.3% in terms of the execution time.

• The Journal of the Acoustical Society of Korea
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• v.23 no.5
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• pp.420-427
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• 2004

This paper presents real time implementation of 4kbps EHSX (Enhanced Harmonic Stochastic Excitation) speech coder that combines the harmonic vector excitation coding with time-separated transition coding. The harmonic vector excitation coding uses the harmonic excitation coding for voiced frames and used the vector excitation coding with the structure of analysis-by-synthesis for unvoiced frames, respectively. For transition frames mixed with voiced and unvoiced signal, we use the time-separated transition coding. In this paper. we present the optimization methods of implementation speech coder on the EMS320C6701/sup (R)/ DSP. To reduce the complex for real-time implementation. we perform the optimization method in algorithm by replacing the complex sinusoidal synthesis method with IFFT. and we apply fully pipelines hand assembly coding after converting it from floating source to fixed source. To generate a more efficient code. we also make use or the available EMS320C6701/sup (R)/ resources such as Fastest67x library and memory organization.

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.134-140
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• 2006

This paper proposed a low power resource allocation algorithm for the minimum switching activity of operators in high level synthesis. In this paper, the proposed method finds switching activity in circuit each functional unit exchange for binary sequence length and value bit are logic one value. To use the switching activity was found the allocation with minimal power consumption, the proposed method visits all control steps one by one and determines the allocation with minimal power consumption at each control step. As the existing method, the execution time can be fast according to use the number of operator and maximal control step. And it is the reduction effect from 8.5% to 9.3%.

• Journal of the Korea Computer Graphics Society
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• v.20 no.2
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• pp.25-32
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• 2014

We present an example-based approach to synthesizing physically simulated Rube Goldberg machines in which a series of rigid body elements are sequentially triggered and driven along the causal chain. Given a set of elements, our goal is to automatically instantiate and arrange those elements to meet the user-specified requirements including the start and end positions, and the boundary of movement. To do so, we first sample small-scale machines consisting of only a few elements randomly, and represent the connectivity between every pair of components as a graph structure. Searching over possible paths in this graph solves our problem by finding a path that can be unrolled to satisfy the given requirements, and then assembling components sequentially along the solution path. In order to ensure that the machine works precisely in a physically simulated environment, we finally elaborate the layout of assembled components by a simple greedy algorithm. We demonstrate the usefulness of our approach by displaying a large diversity of Rube Goldberg machines built with only five kinds of elements.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.2
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• pp.375-384
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• 2016

In this paper, when stereo image, satellite view and corresponding depth maps were used as the input data, we propose a new method that convert these data to data format suitable for compressing, and then by using these format, intermediate view is synthesized. In the transmitter depth maps are merged to a global depth map and satellite view are converted to residual image corresponding hole region as out of frame area and occlusion region. And these images subsampled to reduce a mount of data and stereo image of main view are encoded by HEVC codec and transmitted. In the receiver intermediate views between stereo image and between stereo image and bit-rate are synthesized using decoded global depth map, residual images and stereo image. Through experiments, we confirm good quality of intermediate views synthesized by proposed format subjectively and objectively in comparison to intermediate views synthesized by MVD format versus total bit-rate.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11C
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• pp.1541-1550
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• 2004

In this paper, we propose an advanced hardware architecture for fast multi-resolution motion estimation of the video coding standard MPEG-1,2 and MPEG-4 AVC. We describe the algorithm and derive hardware architecture emphasizing the importance of area for low cost and fast operation by using the shared memory, the special ram architecture, the motion vector for 4 pixel x 4 pixel, the spiral search and so on. The proposed architecture has been verified by ARM-interfaced emulation board using Excalibur Altera FPGA and also by ASIC synthesis using Samsung 0.18 m CMOS cell library. The ASIC synthesis result shows that the proposed hardware can operate at 140 MHz, processing more than 1,100 QCIF video frames or 70 4CIF video frames per second. The hardware is going to be used as a core module when implementing a complete MPEG-4 AVC video encoder ASIC for real-time multimedia application.

• The Journal of the Korea institute of electronic communication sciences
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• v.17 no.2
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• pp.333-342
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• 2022

Cellular Automata (CA) is a discrete and abstract computational model that is being applied in various fields. Applicable as an excellent pseudo-random sequence generator, CA has recently developed into a basic element of cryptographic systems. Several studies on CA-based stream ciphers have been conducted and it has been observed that the encryption strength increases when the radius of a CA's neighbor is increased when appropriate CA rules are used. In this paper, among CAs that can be applied as a one-dimensional pseudo-random number sequence generator (PRNG), one-dimensional 5-neighbor CAs are classified according to the connection state of their neighbors, and the ignition relationship of the characteristic polynomial is obtained. Also this paper propose a synthesis algorithm for an asymmetric 1-D linear 5-neighbor MLCA in which the radius of the neighbor is increased by 2 using the one-dimensional 3-neighbor 90/150 CA state transition matrix.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.80-89
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• 2000

In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the$^1$costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that it fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs by 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.