• Journal of the Korean Operations Research and Management Science Society
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• v.24 no.2
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• pp.81-94
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• 1999

ATM network design procedure is different from the current circuit or packet networks design procedure because of the variety of the offered services and the variability of requested bandwidth for each connection of ATM network. A number of optimization models for the link dimensioning of ATM network design have been proposed in the literature. However, most of the literature did not consider the modularity of resources allocated to a transmission path and the non-bifurcation of a VP link over the more than one TP, which are standardized in recent ITU-T Recommendations. In thIs paper, we propose a mathematical model for link dimensioning of ATM networks, based on the network synthesis method and a generalized bin-packing problem. The suggested model satisfies the constraints mentioned in the ITU-T Recommendations. We also propose efficient and practical algorithms for the suggested model. Computational experiment shows that the suggested algorithm gives efficient solutions even for moderate and large-sized networks within reasonable time.

• Proceedings of the Korean Information Science Society Conference
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• 2002.04a
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• pp.19-21
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• 2002

우리는 저전력 소모를 위한 상위 수준(high-level)에서의 효과적인 바인딩(binding) 알고리즘을 제안한다. 이전 연구들에 의해서 저전력 소모를 위한 몇몇의 바인딩 알고리즘들은 멀티-코모도티 플로우(multi-commodity flow) 문제로 모델링 될 수 있음이 밝혀졌다. 그러나 멀티-코모도티 플로우 문제는 NP-hard이기 때문에 진은 크기의 설계에만 적용될 수 있다. 이러한 제약을 극복하기 위해 우리는 네트워크 상의 플로우를 잘 이용해서 효과적으로 빠른 시간 안에 최적에 가까운 결과를 낼 수 있는 방법을 제안하여 크기가 큰 설계에도 적용할 수 있도록 한다. 이를 위해 우리는 첫번째 단계에서는 네트워크에서 최소 비용의 최대 플로우 (maximum f1ow -minimum cost)를 구하는 방법을 부분적으로 이용해서 유효한 결과를 구하고 두 번째 단계에서는 이를 반복적으로 개선시켜나가는 2 단계의 알고리즘을 제안한다. 벤치마크를 이용한 실험 결과는 제안된 알고리즘이 실제적인 설계에 적용되었을때, 충분히 빠른 시간 안에 최적에 가까운 결과를 생성함을 보여준다.

• Proceedings of the Korean Information Science Society Conference
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• 2003.04c
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• pp.283-285
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• 2003

We have developed an optimization algorithm based formulation for performing efficient time driven simultaneous place and route for FPGAS. Field programmable gate array(FPGAS) provide of drastically reducing the turn-around time for digital ICs, with a relatively small degradation in performance. For a variety of application specific Integrated circuit application, where time-to-market is most critical and the performance requirement do not mandate a custom or semicustom approach, FPGAS are an increasingly popular alternative. This has prompted a substantial amount of specialized synthesis and layout research focused on maximizing density, minimizing delay, and minimizing design time.

• Journal of the Korean Society for Precision Engineering
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• v.23 no.6 s.183
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• pp.72-80
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• 2006

Electric Power Steering (EPS) mechanism has become widely equipped in passenger vehicle due to the increasing environmental concerns and higher fuel efficiency. This paper describes the development of concurrent simulation technique and simulation integration technique of EPS control system with a dynamic vehicle system. A full vehicle model interacting with EPS control algorithm was concurrently simulated on a single bump road condition. The dynamic responses of vehicle chassis and steering system resulting from road surface impact were evaluated and compared with proving ground experimental data. The comparisons show reasonable agreement on tie-rod load, rack displacement, steering wheel torque and tire center acceleration. This concurrent simulation capability was employed fur EPS performance evaluation and calibration as well as for vehicle handling performance integration and synthesis.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1960-1961
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• 2011

얼굴 인식에서 가장 많이 사용되고 있는 PCA(Principal Component Analysis)는 고차원의 얼굴 데이터를 낮은 차원으로 표현할 수 있다는 장점이 있다. LDA(Linear Discriminant Analysis)는 서로 다른 데이터를 잘 분리할 수 있으며, 얼굴 인식에서 우수한 성능을 보인다. 본 연구에서는 서로의 장점을 결합하여 PCA와 LDA를 혼합, 적용하였다. 고차원의 얼굴데이터를 PCA로 차원 축소한 후 LDA를 이용해 더욱 효과적인 분류가 되어 얼굴 인식률을 향상시킨다. 인식 모듈로는 pRBFNN(Polynomial Based Radial Basis Function Neural Networks) 모델을 구축하여 고차원 패턴인식 문제에 대한 해결책을 제시하고자 한다. 그리고 제안된 패턴분류기는 얼굴 데이터를 사용하여 성능을 확인한다.

• International Journal of Contents
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• v.9 no.1
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• pp.33-37
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• 2013

BCH code is one of the most widely used error correcting code for the detection and correction of random errors in the modern digital communication systems. The conventional BCH encoder that is operated in bit-serial manner cannot adequate with the recent high speed appliances. Therefore, parallel encoding algorithms are always a necessity. In this paper, we introduced a new systolic array type BCH parallel encoder. To study the area and speed, several parallel factors of the systolic array encoder is compared. Furthermore, to prove the efficiency of the proposed algorithm using tree-type structure, the throughput and the area overhead was compared with its counterparts also. The proposed BCH encoder has a great flexibility in parallelization and the speed was increased by 40% than the original one. The results were implemented on synthesis and simulation on FPGA using VHDL.

• Journal of KIISE:Computer Systems and Theory
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• v.27 no.12
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• pp.981-987
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• 2000

이 논문은 상위 단계 데이터-경로 합성에서 연산 스케쥴링과 자원 할당 및 배정을 동시에 고려한 통합적 접근 방법을 제시한다. 제안한 방법은 스케쥴링 되어있지 않은 데이터-플로우 그래프에 대해서 수행에 필요한 총 clock 스텝 수와 필요한 회로 면적을 동시에 최소화하는 데이터-경로 생성에 특징이 있다. 일반적으로, 연결선의 결정이 합성의 마지막 단계에서 이루어지는 기존의 방법과는 다르게, 우리의 접근 방법은 연산 스케쥴링과 연산의 연산 모듈 배정 그리고 변수의 레지스터 배정 작업을 동시에 수행하여 추가적인 연결선의 수를 매 clock 스텝마다 최적화(optimal) 시킨다. 본 논문은, 이 문제를 최소-비용의 최대-플로우 문제로 변형하여 minimum cost augmentation 방법으로 polynomial time 안에 해결하는 알고리즘을 제안한다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.4
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• pp.424-432
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• 1992

This paper deals with the scheduling ploblems, which are the most important subtasks in High-level syntheses. IP(integer programming) formulations is used as the scheduling problem approach. This paper describes a new resource-constraints scheduling algorithm. We have concentrated our attentions on the multicycle operations and the structural pipelining, and we fully analyze the characteristics of operators to achieve the maximal performance and the maximal resource sharing. For experiment results, we choose the 5-th order digital wave filter as a benchmark and do the schedule, Finally, we can obtain near-optimal scheduling results.

• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.52-55
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• 1996

In order to establish the robust current controller design technique of series wound motor driver system. This paper proposes a method of compensated Bang-Bang current control using a series wound motor driver system under improperly variable load. To get minimum time torque control. A compensated Bang-Bang current controller structure is simpler than the structure of PID plus Bang-Bang controller. This paper shows that a general 8 bits microprocessor be used efficiently implementing such an algorithm. The calculation time of software is extremely small when compared with conventional PID plus Bang-Bang a controller. Both nonlinear operating characteristics of Digital switching elements and Describing Function methods are used for the analysis and synthesis. Real time implementation of compensated Bang-Bang current is achieved. Concept design strategy of the control and PWM waveform generation algorithms are presented in the paper.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.1
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• pp.101-109
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• 2017

This paper presents a high-throughput low-complexity 512-point eight-parallel mixed-radix multipath delay feedback (MDF) fast Fourier transform (FFT) processor architecture for orthogonal frequency division multiplexing (OFDM) applications. To decrease the number of twiddle factor (TF) multiplications, a mixed-radix $2^4/2^3$ FFT algorithm is adopted. Moreover, a dual-path shared canonical signed digit (CSD) complex constant multiplier using a multi-layer scheme is proposed for reducing the hardware complexity of the TF multiplication. The proposed FFT processor is implemented using TSMC 90-nm CMOS technology. The synthesis results demonstrate that the proposed FFT processor can lead to a 16% reduction in hardware complexity and higher throughput compared to conventional architectures.