• 한국지능시스템학회논문지
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• 제14권2호
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• pp.216-221
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• 2004

This paper describes an optimal synthesis method of binary neural network for pattern recognition. Our objective is to minimize the number of connections and the number of neurons in hidden layer by using a Newly Expanded and Truncated Learning Algorithm (NETLA) for the multilayered neural networks. The synthesis method in NETLA uses the Expanded Sum of Product (ESP) of the boolean expressions and is based on the multilayer perceptron. It has an ability to optimize a given binary neural network in the binary space without any iterative learning as the conventional Error Back Propagation (EBP) algorithm. Furthermore, NETLA can reduce the number of the required neurons in hidden layer and the number of connections. Therefore, this learning algorithm can speed up training for the pattern recognition problems. The superiority of NETLA to other learning algorithms is demonstrated by an practical application to the approximation problem of a circular region.

• Journal of Electrical Engineering and information Science
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• 제3권1호
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• pp.1-7
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• 1998

High-Level synthesis of digital circuits calls for automatic translation of a behavioral description to a structural design entity represented in terms of components and connection. One of the critical steps in high-level synthesis is to determine a particular scheduling algorithm that will assign behavioral operations to control states. A new scheduling algorithm called Data Availability Scheduling (DAS) for high-level synthesis is presented. It can determine an appropriate scheduling algorithm and minimize the number of states required using data availability and dependency conditions extracted from the behavioral code, taking into account of states required using data availability and dependency conditions extracted from the behavioral code, taking into account resource constraint in each control state. The DAS algorithm is efficient because data availability conditions, and conditional and wait statements break the behavioral code into manageable pieces which are analyzed independently. The output is the number of states in a finite state machine and shows better results than those of previous algorithms.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
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• pp.188-191
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• 2000

This paper presents a register scheduling and allocation algorithm for high level synthesis. The proposed algorithm executes the low power scheduling to reduce the switching activity using shut down technique which was not unnecessary the calculation through the extraction DFG from VHDL description. Also, the register allocation algorithm determines the minimum register after the life time analysis of all variable. It is minimum the switching activity using graph coloring technique for low power consumption. The proposed algorithm proves the effect through various filter benchmark to adopt a new scheduling and allocation algorithm considering the low power.

• 전자공학회논문지B
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• 제31B권3호
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• pp.24-38
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• 1994

In this paper we develop the software simulator written in a C language for a frequency modulation synthesis and the approximate range of parameters, for a musically satisfactory timbre, obtained by using the software simulator will be applied to develop an algorithm for parameter extraction. For a frequency modulation synthesis, we also develop an algorithm for parameter extraction through waveform analysis in the time domain as well as spectrum analysis using a FFT in the frequency domain. To verify the validity of the developed algorithm as well as software simulator experimentally, we extract parameters for the several music instruments using the suggested algorithm and analyze the synthesized sound by applying the parameters to the software simulator. The evaluation of the synthesized sound is first done by listening the sound directly as a subjective testing. Secondly, to evaluate the synthesized sound objectively with an engineering sense, we compare the synthesized sound with an original one in a time domain and a frequency domain.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.101-104
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• 2002

This paper propose that is algorithm of power dissipation reduction in the high level synthesis design for DSP(Digital Signal Processor), as the portable terminal system recently demand high power dissipation. This paper obtain effect of power dissipation reduction and switching activity that increase correlation of operands as input data of function unit. The algorithm search loop or repeatedly data to the input operands of function unit. That can be reduce the power dissipation using the new low power high level synthesis algorithm. In this Paper, scheduling operation search same nodes from input DFG(Data Flow Graph) with correlation coefficient of first input node and among nodes. Function units consist a multiplier, an adder and a register. The power estimation method is added switching activity for each bits of nodes. The power estimation have good efficient using proposed algorithm. This paper result obtain more Power reduction of fifty percents after using a new low power algorithm in a function unit as multiplier.

• International Journal of Contents
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• 제7권3호
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• pp.19-28
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• 2011

This paper presents a fast and practical motion synthesis algorithm for massive number of quadruped animals. The algorithm constructs so called speed maps that contain a set of same style motions but different speed from a single cyclic motion by using IK(Inverse Kinematics) solver. Then, those speed maps are connected each other to form a motion graph. At run time, given a point trajectory that obtained from user specification or simulators, the algorithm retrieves proper speed motions from the graph, and modifies and stitches them together to create a long seamless motion in real time. Since our algorithm mainly targets on the massive quadruped animal motions, the motion graph create wide variety of different size of characters for each trajectory and automatically adjusted synthesized motions without causing artifact such as foot skating. The performance of algorithm is verified through several experiments

• 융합신호처리학회 학술대회논문집
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• 한국신호처리시스템학회 2001년도 하계 학술대회 논문집(KISPS SUMMER CONFERENCE 2001
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• pp.73-76
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• 2001

High-level synthesis(HLS)는 주어진 동작(behavior)과 면적(area), 성능(performance), 전력 소비량, 패키징, 테스팅등의 주어진 제한을 만족하게 구현된 구조적 디자인을 생성한다. 즉 high-level synthesis란 디지털 시스템의 알고리즘 단계 서술로부터 레지스터 전달구조의 구현에 이르는 과정을 의미한다. 이러한 high-level synthesis의 과정은 컴파일, 분할(partitioning), 스케줄링(scheduling)등의 단계를 거쳐 디지털 시스템을 설계할 수 있다. 본 논문에서는 high-level synthesis의 단계 중 스케줄링 과정에서 제한조건이 실리콘 면적으로 주어지는 경우에 최적의 functional unit의 수를 찾아내어 최소의 control step에 효과적으로 스케줄링 가능한 알고리즘을 제안하였다.

• 융합신호처리학회논문지
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• 제10권2호
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• pp.141-145
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• 2009

본 논문에서는 입력 동작에 대하여 상위수준 합성을 수행한 후, 합성결과를 SystemC 코드로 전환하는 C-to-SystemC 합성기를 설계 및 구현하였다. 구현된 합성기의 처리과정은 C 소스코드로 기술된 입력 동작을 list 스케줄링 알고리즘을 이용하여 스케줄링한 후, 스케줄링 결과에 left-edge 알고리즘을 이용하여 레지스터 할당을 수행한다. 레지스터 할당 정보를 이용하여 합성기는 채널 및 포트와 같은 SystemC 특성들로 표현된 SystemC 모듈의 코드를 최종적으로 생성한다. C-to-SystemC 합성기의 동작은 EWF(elliptic wave filter)의 합성결과인 SystemC 모듈의 코드를 시뮬레이션하여 검증한다. C-to-SystemC 합성기는 SystemC 설계방법론의 모델링단계부터 합성단계에 이르는 툴 체인의 한 부분으로 사용될 수 있으며, 생성된 SystemC 모듈은 C 모듈에 비해 재사용이 용이하고 다른 SystemC 모듈과 SystemC 채널을 통하여 별도의 추가처리 없이 통신할 수 있다.

• 전자공학회논문지A
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• 제31A권12호
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• pp.122-134
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• 1994

Design of a heuristic algorithm for high level synthesis of multichip architecture is presented in this paper. Considering the design constraints: individual chip area, I/O pin counts, chip-to-chip interconnection counts, interchip communication delay, and chip latecy, the proposed system automatically generates pipelined multichip architectures from behavioral descriptions. For efficient mulichip synthesis, a new methodology is proposed, which performs partitioning and schedulting of SFG into multichip architectures simultaneously. Experimental results for several benchmark programs show that the systems can be used for designing multichip hardware efficiently.

• 대한음성학회지:말소리
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• 제56호
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• pp.225-235
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• 2005

Speech unit concatenation with a large database is presently the most popular method for speech synthesis. In this approach, the mismatches at the unit boundaries are unavoidable and become one of the reasons for quality degradation. This paper proposes an algorithm to reduce undesired discontinuities between the subsequent units. Optimal matching points are calculated in two steps. Firstly, the fullback-Leibler distance measurement is utilized for the spectral matching, then the unit sliding and the overlap windowing are used for the waveform matching. The proposed algorithm is implemented for the corpus-based unit concatenating Korean text-to-speech system that has an automatically labeled database. Experimental results show that our algorithm is fairly better than the raw concatenation or the overlap smoothing method.