• International Journal of Control, Automation, and Systems
• /
• 제6권2호
• /
• pp.171-179
• /
• 2008

This paper addresses the synthesis of an iterative learning controller for a class of linear systems with norm-bounded parameter uncertainties. We take into account an iterative learning algorithm with current cycle feedback in order to achieve both robust convergence and robust stability. The synthesis problem of the developed iterative learning control (ILC) system is reformulated as the ${\gamma}$-suboptimal $H_{\infty}$ control problem via the linear fractional transformation (LFT). A sufficient convergence condition of the ILC system is presented in terms of linear matrix inequalities (LMIs). Furthermore, the ILC system with fast convergence rate is constructed using a convex optimization technique with LMI constraints. The simulation results demonstrate the effectiveness of the proposed method.

• 전자공학회논문지B
• /
• 제31B권8호
• /
• pp.87-98
• /
• 1994

Object-oriented analysis-synthesis coding subdivides each image of a sequence into moving objects and compensates the motion of each object. Thus it can reconstruct real motion better than conventional motion-compensated coding techniques at very-low-bit-rates. It uses a mapping parameter technique for estimating motion information of each object. Since a mapping parameter technique uses gradient operators it is sensitive to redundant details and noise. To accurately determine mapping parameters, we propose a new analysis method using integral projections for estimation of gradient values. Also to reconstruct correctly the local motion the proposed algorithm divides an image into segmented objects each of which having uniform motion information while the conventional one assumes a large object having the same motion information. Computer simulation results with several test sequences show that the proposed image analysis method in object-oriented analysis-synthesis coding shows better performance than the conventional one.

• 한국정보전자통신기술학회논문지
• /
• 제4권2호
• /
• pp.83-87
• /
• 2011

상위수준합성에서 클록 선택은 시스템의 성능과 설계의 질에 큰 영향을 미친다. 대부분의 시스템에서 클럭은 사전에 설계자에 의해 미리 명시되어야하지만, 최상의 클록은 상이한 스케줄의 결과를 평가한 후에 탐색이 가능하다. 본 연구에서는 체이닝이 가능한 연산 집합으로부터 클록을 선택하면서 동시에 스케줄링 하는 방법을 제안한다. 제안 스케줄링 알고리즘은 선택된 클록 주기에 기초하여 비트 단위 지연시간을 고려한 체이닝을 수행하며 리스트 스케줄링 방법으로 진행한다. 실험 결과는 제안 방법이 18%의 성능 개선이 있음을 보인다.

• 전자공학회논문지A
• /
• 제30A권6호
• /
• pp.49-57
• /
• 1993

In the paper, we describe the design of a pipelined datapath synthesis system for DSP applications. Taking SFG (Signal Flow Graph) in schematic as inputs, the system generates pipelined datapaths automatically through scheduling and module allocation processes. For efficient hardware synthesis, scheduling and module allocation algorithms are proposed. The proposed scheduling algorithm is of iterative/constructive nature, where the measure of equi-distribution of operations to partitions is adopted as the objective function. Module allocation is performed to reduce the interconnection cost from the initial allocation. In the experiment, we compare the results with those of other systems and show the effectiveness of the proposed algorithms.

• 전자공학회논문지C
• /
• 제34C권6호
• /
• pp.1-10
• /
• 1997

By considering low power design at higher levels of abstraction rather than at lower levels of abstraction, we can apply various transformation techniques to a system design with wider view and obtain much more effective power reduction with less cost and effort. In this paper, a transformation technique, called power - conscious loop folding is proposed for high level synthesis of a low power system.Our work is focused on reducing the power consumed by functional units in adata path dominated circuit through the decrease of switching activity. Te transformation algorithm has been implemented and integrated into HYPER, a high level synthesis system for experiments. In our experiments, we could achieve a pwoer reduction of up to 50% for data path dominated circuits.

• 한국지능시스템학회:학술대회논문집
• /
• 한국퍼지및지능시스템학회 1993년도 Fifth International Fuzzy Systems Association World Congress 93
• /
• pp.1321-1325
• /
• 1993

This paper investigates the use of Fuzzy vector quantizer(FVQ) in speech synthesis. To compress speech data, we employ K-means algorithm to design codebook and then FVQ technique is used to analysize input speech vectors based on the codebook in an analysis part. In FVQ synthesis part, analysis data vectors generated in FVQ analysis is used to synthesize the speech. We have fined that synthesized speech quality depends on Fuzziness values in FVQ, and the optimum fuzziness values maximized synthesized speech SQNR are related with variance values of input speech vectors. This approach is tested on a sentence, and we compare synthesized speech by a convensional VQ with synthesized speech by a FVQ with optimum Fuzziness values.

• 한국멀티미디어학회논문지
• /
• 제11권6호
• /
• pp.729-736
• /
• 2008

Using video synthesis to depict flowing water is useful in virtual reality, computer games, digital movies and scientific computing. This paper presents a novel algorithm for synthesizing dynamic water scenes through a sample video based on a dynamic texture model. In the paper, we treat the video sample as a 2-D texture image. In order to obtain textons, we analyze the video sample automatically based on dynamic texture model. Then, we utilize a linear dynamic system (LDS) to describe the characteristics of each texton. Using these textons, we synthesize a new video for dynamic flowing water which is prolonged and non-fuzzy in vision. Compared with other classical methods, our method was tested to demonstrate the effectiveness and efficiency with several video samples.

• 제어로봇시스템학회논문지
• /
• 제8권8호
• /
• pp.706-712
• /
• 2002

In general, a deadlock in flexible manufacturing systems (FMSs) is caused by a resource limitation and the diversity of routings. However, the deadlock of industrial controllers such as programmable logic controllers (PLCs) can occur from different causes compared with those in general FMSs. The deadlock of PLCs is usually caused by an error signal between PLCs and manufacturing systems. In this paper, we propose a deadlock detection and recovery (DDR) algorithm to resolve the deadlock problem of PLCs at design stage. This paper employs the MAPN (modified automation Petri net), MTPL (modified token passing logic), and ECC (efficient code conversion) algorithm to model manufacturing systems and to convert a Petri net model into a desired LD (ladder diagram). Finally, an example of manufacturing systems is provided to illustrate the proposed DDR algorithm.

• 한국소음진동공학회:학술대회논문집
• /
• 한국소음진동공학회 2003년도 춘계학술대회논문집
• /
• pp.514-519
• /
• 2003

The aircraft engine is usually supported by rolling element bearings and has a small damping rate, which is vol y sensitive to external force. The high-performance requirement of the rotors leads to complex assembly designs and are more flexible. Squeeze film dampers (SFDs) are introduced to provide damping while crossing the critical speeds and stability to the rotor s :stem. Hence, the focus of the present investigation is on the decision of an optimal size of the flexible rotor system supported by the squeeze film dampers to minimize the maximum transmitted load and unbalance response over a range operating speeds. The enhanced genetic algorithm (EGA), which was developed by authors, is used in the optimization process. This algorithm is based on the synthesis of a modified genetic algorithm and simplex method. The results show significant benefits in using EGA when compared with nonlinear programming (NLP).

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2004년도 학술대회지
• /
• pp.509-513
• /
• 2004

An area of research called evolvable hardware (EHW) has recently emerged which combines aspects of evolutionary computation with hardware design and synthesis. The features that can be used to identify and classify evolvable hardware are the evolutionary algorithm, the implementation and the genotype representation. This paper gives an introduction to the field. It continues by including classifying the EHW and the applications of the area.