• 제목/요약/키워드: synthesis algorithm

검색결과 668건 처리시간 0.028초

고속전철 객차를 위한 유한요소모델링 및 모드합성기법의 개발 (The Development of a finite-Element Modelling and Component Mode Synthesis Method for High-Speed railway Passenger Cars)

  • 장경진;김홍준;이상민;박영필
    • 한국철도학회:학술대회논문집
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    • 한국철도학회 1998년도 창립기념 춘계학술대회 논문집
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    • pp.233-240
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    • 1998
  • In the design of the high-speed railway vehicles of low noise and vibration characteristics, it is desirable to develop efficient and systematic procedures for analyzing large structures. In this paper, some finite-element modelling techniques and an efficient analytical method are proposed for this purpose. The analytical method is based on substructuring approach such as a free-interface method and a generalized synthesis algorithm. In final, the proposed approaches are applied to the finite-element modelling, modal analysis and subsequent model updating procedures of the high-speed railway intermediate trailers.

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이산현상시스템의 관리제어기법에 관한 연구 - 분산시스템의 병렬제어 응용 - (Supervisory Control of Discrete Event Systems)

  • 이준화;권욱현
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1993년도 하계학술대회 논문집 A
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    • pp.310-312
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    • 1993
  • We present the discrete event systems modeled by finite state machines in this paper using the boolean matrices and vectors. We propose a supervisor synthesis method for such boolean discrete-event systems. The proposed supervisor synthesis algorithm is practically implementable, since the size of the state vector in the product system does not increase exponentially with the number of components.

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제한조건을 고려한 효율적 회로 설계 알고리즘 (An efficient circuit design algorithm considering constraint)

  • 김재진
    • 디지털산업정보학회논문지
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    • 제8권1호
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    • pp.41-46
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    • 2012
  • In this paper, An efficient circuit design algorithm considering constraint is proposed. The proposed algorithm sets up in time constraint and area constraint, power consumption constraint for a circuit implementation. First, scheduling process for time constraint. Select the FU(Function Unit) which is satisfied with time constraint among the high level synthesis results. Analyze area and power consumption of selected FUs. Constraint set for area and power constraint. Device selection to see to setting condition. Optimization circuit implementation in selected device. The proposed algorithm compared with [7] and [8] algorithm. Therefore the proposed algorithm is proved an efficient algorithm for optimization circuit implementation.

$H_{\infty}$ 최적 제어기 구성을 위한 개선된 알고리즘 (Advanced Algorithm for $H_{\infty}$ Optimal controller synthesis)

  • 김용규;양도철;유창근;장호성
    • 대한전자공학회:학술대회논문집
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    • 대한전자공학회 2002년도 하계종합학술대회 논문집(5)
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    • pp.149-152
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    • 2002
  • The aim of this study is to analyse the problems occurred by using classical algorithm to synthesize the H$\infty$ optimal controller. The obtained result of analysis applied to the composition of algorithm for the new H$\infty$ optimal controller which was introduced in this study. The study investigates and compares H$\infty$ optimal controller formed by new algorithm with the one formed by classical algorithm. In particular, robustness related to the robust control is systematically described by using the composition of algorithm for the classical H$\infty$ optimal controller. In addition, the flow charts classified into classical algorithm and new one are discussed to synthesize the H$\infty$ optimal controller.

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Improvement of the classiest algorithm for H-infini optimization synthesis

  • Kim, Yong-Kyu;Ryu, Chang-Keun;yang, Doh-Chul
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2002년도 ICCAS
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    • pp.59.1-59
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    • 2002
  • . Contents 1 : Abstract and Introduction . Contents 2 : Choose the weighting function . Contents 3 : H-infini Optimization and Simulation . Contents 4 : Conclusion and Reference

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가상시점 영상 생성을 위한 경계 잡음 제거와 홀 채움 기법 (Boundary Noise Removal and Hole Filling Algorithm for Virtual Viewpoint Image Generation)

  • 고민수;유지상
    • 한국통신학회논문지
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    • 제37권8A호
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    • pp.679-688
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    • 2012
  • 본 논문에서는 3D 워핑(warping) 기법을 이용하여 가상시점 영상생성 시 화질 개선을 위하여 경계 잡음(boundary noise)을 제거하고 홀(hole) 채움을 하는 새로운 기법을 제안한다. 경계 잡음은 가상시점 영상 합성 시기준 시점 영상과 깊이 영상 내 객체의 경계 불일치로 발생되며 홀은 기준시점 영상에서 보상할 수 없는 가려짐 영역(occlusion)으로 정의된다. 제안하는 기법에서는 경계 잡음 제거를 위해 먼저 배경 화소들의 평균과 절대 값 비교를 통해 경계 잡음에 해당되는 화소를 검출하고 검출된 화소를 홀 영역으로 확장한다. 경계 잡음 영역이 포함된 확장된 홀 영역은 나선형 가중 평균(spiral weighted average) 기법과 기울기 탐색(gradient searching) 기법을 혼용하여 채우게 된다. 나선형 가중 평균 기법은 깊이 정보를 사용함으로 객체 정보를 최소로 사용하지만 결과 영상이 번지는 단점이 있다. 기울기 탐색 기법은 영상의 기울기를 이용하여 세밀한 부분을 보존할 수 있는 장점이 있다. 따라서 각각의 결과를 ${\alpha}$ 가중치로 조합하여 생성된 가상 시점은 두 기법의 장점을 동시에 적용하기 때문에 좋은 화질을 얻을 수 있다. 실험을 통해 제안하는 기법의 성능이 기존의 다른 기법보다 우수하다는 것을 확인하였다.

A Face Tracking Algorithm for Multi-view Display System

  • Han, Chung-Shin;Go, Min Soo;Seo, Young-Ho;Kim, Dong-Wook;Yoo, Ji-Sang
    • IEIE Transactions on Smart Processing and Computing
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    • 제2권1호
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    • pp.27-35
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    • 2013
  • This paper proposes a face tracking algorithm for a viewpoint adaptive multi-view synthesis system. The original scene captured by a depth camera contains a texture image and 8 bit gray-scale depth map. From this original image, multi-view images that correspond to the viewer's position can be synthesized using geometrical transformations, such as rotation and translation. The proposed face tracking technique gives a motion parallax cue by different viewpoints and view angles. In the proposed algorithm, the viewer's dominant face, which is established initially from a camera, can be tracked using the statistical characteristics of face colors and deformable templates. As a result, a motion parallax cue can be provided by detecting the viewer's dominant face area and tracking it, even under a heterogeneous background, and synthesized sequences can be displayed successfully.

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병렬처리를 위한 고속 Ray Tracing 프로세서의 설계 (Implementation of Ray Tracing Processor for the Parallel Processing)

  • 최규열;정덕진
    • 대한전기학회논문지:전력기술부문A
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    • 제48권5호
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    • pp.636-642
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    • 1999
  • The synthesis of the 3D images is the most important part of the virtual reality. The ray tracing is the best method for reality in the 3D graphics. But the ray tracing requires long computation time for the synthesis of the 3D images. So, we implement the ray tracing with software and hardware. Specially we design the hit-test unit with FPGA tool for the ray tracing. Hit-test unit is a very important part of ray tracing to improve the speed. In this paper, we proposed a new hit-test algorithm and apply the parallel architecture for hit-test unit to improve the speed. We optimized the arithmetic unit because the critical path of hit-test unit is in the multiplication part. We used the booth algorithm and the baugh-wooley algorithm to reduce the partial product and adapted the CSA and CLA to improve the efficiency of the partial product addition. Our new Ray tracing processor can produce the image about 512ms/F and can be adapted to real-time application with only 10 parallel processors.

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