• Proceedings of the KSR Conference
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• 1998.05a
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• pp.233-240
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• 1998

In the design of the high-speed railway vehicles of low noise and vibration characteristics, it is desirable to develop efficient and systematic procedures for analyzing large structures. In this paper, some finite-element modelling techniques and an efficient analytical method are proposed for this purpose. The analytical method is based on substructuring approach such as a free-interface method and a generalized synthesis algorithm. In final, the proposed approaches are applied to the finite-element modelling, modal analysis and subsequent model updating procedures of the high-speed railway intermediate trailers.

• Proceedings of the KIEE Conference
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• 1993.07a
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• pp.310-312
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• 1993

We present the discrete event systems modeled by finite state machines in this paper using the boolean matrices and vectors. We propose a supervisor synthesis method for such boolean discrete-event systems. The proposed supervisor synthesis algorithm is practically implementable, since the size of the state vector in the product system does not increase exponentially with the number of components.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.1
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• pp.41-46
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• 2012

In this paper, An efficient circuit design algorithm considering constraint is proposed. The proposed algorithm sets up in time constraint and area constraint, power consumption constraint for a circuit implementation. First, scheduling process for time constraint. Select the FU(Function Unit) which is satisfied with time constraint among the high level synthesis results. Analyze area and power consumption of selected FUs. Constraint set for area and power constraint. Device selection to see to setting condition. Optimization circuit implementation in selected device. The proposed algorithm compared with [7] and [8] algorithm. Therefore the proposed algorithm is proved an efficient algorithm for optimization circuit implementation.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.149-152
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• 2002

The aim of this study is to analyse the problems occurred by using classical algorithm to synthesize the H$\infty$ optimal controller. The obtained result of analysis applied to the composition of algorithm for the new H$\infty$ optimal controller which was introduced in this study. The study investigates and compares H$\infty$ optimal controller formed by new algorithm with the one formed by classical algorithm. In particular, robustness related to the robust control is systematically described by using the composition of algorithm for the classical H$\infty$ optimal controller. In addition, the flow charts classified into classical algorithm and new one are discussed to synthesize the H$\infty$ optimal controller.

• 한국가스학회:학술대회논문집
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• 1998.09a
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• pp.25-30
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• 1998

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.59.1-59
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• 2002

. Contents 1 : Abstract and Introduction . Contents 2 : Choose the weighting function . Contents 3 : H-infini Optimization and Simulation . Contents 4 : Conclusion and Reference

• 한국가스학회:학술대회논문집
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• 1999.09a
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• pp.244-249
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• 1999

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.8A
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• pp.679-688
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• 2012

In this paper, performance improved hole-filling algorithm including boundary noise removing pre-process which can be used for an arbitrary view synthesis with given two views is proposed. Boundary noise usually occurs because of the boundary mismatch between the reference image and depth map and common-hole is defined as the occluded region. These boundary noise and common-hole created while synthesizing a virtual view result in some defects and they are usually very difficult to be completely recovered by using only given two images as references. The spiral weighted average algorithm gives a clear boundary of each object by using depth information and the gradient searching algorithm is able to preserve details. In this paper, we combine these two algorithms by using a weighting factor ${\alpha}$ to reflect the strong point of each algorithm effectively in the virtual view synthesis process. The experimental results show that the proposed algorithm performs much better than conventional algorithms.

• IEIE Transactions on Smart Processing and Computing
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• v.2 no.1
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• pp.27-35
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• 2013

This paper proposes a face tracking algorithm for a viewpoint adaptive multi-view synthesis system. The original scene captured by a depth camera contains a texture image and 8 bit gray-scale depth map. From this original image, multi-view images that correspond to the viewer's position can be synthesized using geometrical transformations, such as rotation and translation. The proposed face tracking technique gives a motion parallax cue by different viewpoints and view angles. In the proposed algorithm, the viewer's dominant face, which is established initially from a camera, can be tracked using the statistical characteristics of face colors and deformable templates. As a result, a motion parallax cue can be provided by detecting the viewer's dominant face area and tracking it, even under a heterogeneous background, and synthesized sequences can be displayed successfully.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.5
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• pp.636-642
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• 1999

The synthesis of the 3D images is the most important part of the virtual reality. The ray tracing is the best method for reality in the 3D graphics. But the ray tracing requires long computation time for the synthesis of the 3D images. So, we implement the ray tracing with software and hardware. Specially we design the hit-test unit with FPGA tool for the ray tracing. Hit-test unit is a very important part of ray tracing to improve the speed. In this paper, we proposed a new hit-test algorithm and apply the parallel architecture for hit-test unit to improve the speed. We optimized the arithmetic unit because the critical path of hit-test unit is in the multiplication part. We used the booth algorithm and the baugh-wooley algorithm to reduce the partial product and adapted the CSA and CLA to improve the efficiency of the partial product addition. Our new Ray tracing processor can produce the image about 512ms/F and can be adapted to real-time application with only 10 parallel processors.