• Journal of KIISE:Software and Applications
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• v.34 no.7
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• pp.635-645
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• 2007

Component technology has been widely accepted as an effective way for building software systems with reusable components, and Microsoft (MS) .NET is one of the recent representative component technologies. Model Driven Architecture (MDA) is a new development paradigm which generates software by transforming design models automatically and incrementally. Transformation of structural models in MDA has been successfully applied. However, transformation of dynamic models and pervasive services, such as transaction service, security service, synchronization service and object pooling are largely remains as an area for further research. The recent enterprise system has multi tier distributed architecture, and the functionality of early mentioned pervasive services is essential for this architecture. .NET platform can implement Component Object Model+ (COM+) component for supporting pervasive services by specify Attribute code. In this paper, we specify the functionalities of the COM+ component offering pervasive services, and then those functionalities are defined by UML profile. By using the profile, the Platform Specific Model (PSM) for .NET/C# is specified, and .NET components are automatically generated through our tool. The development productivity, extensibility, portability, and maintenance of software can be dramatically improved by using of the proposed methods.

• The KIPS Transactions:PartA
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• v.10A no.3
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• pp.247-254
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• 2003

This paper describes a Delay Locked Loop (DLL) with low supply voltage and wide lock range for Synchronous DRAM which employs Double Data Rate (DDR) technique for faster data transmission. To obtain high resolution and fast lock-on time, a new type of phase detector is designed. The new counter and lock indicator structure are suggested based on the Dual-clock dual-data Flip Flop (DCDD FF). The DCDD FF reduces the size of counter and lock indicator by about 70%. The delay line is composed of coarse and fine units. By the use of fast phase detector, the coarse delay line can detect minute phase difference of 0.2 nsec and below. Aided further by the new type of 3-step vernier fine delay line, this DLL circuit achieves unprecedented timing resolution of 25psec. This DLL spans wide locking range from 500MHz to 500MHz and generates high-speed clocks with fast lock-on time of less than 5 clocks. When designed using 0.25 um CMOS technology with 1.8V supply voltage, the circuit consumes 32mA at 500MHz locked condition. This circuit can be also used for other applications as well, such as synchronization of high frequency communication systems.

• KIPS Transactions on Software and Data Engineering
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• v.11 no.10
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• pp.409-418
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• 2022

In this paper, we propose SAAnnot-C3Pap, a semi-automatic annotation method for obtaining ground truth of a player's posture. In order to obtain ground truth about the two-dimensional joint position in the existing music domain, openpose, a two-dimensional posture estimation method, was used or manually labeled. However, automatic annotation methods such as the existing openpose have the disadvantages of showing inaccurate results even though they are fast. Therefore, this paper proposes SAAnnot-C3Pap, a semi-automated annotation method that is a compromise between the two. The proposed approach consists of three main steps: extracting postures using openpose, correcting the parts with errors among the extracted parts using supervisely, and then analyzing the results of openpose and supervisely. Perform the synchronization process. Through the proposed method, it was possible to correct the incorrect 2D joint position detection result that occurred in the openpose, solve the problem of detecting two or more people, and obtain the ground truth in the playing posture. In the experiment, we compare and analyze the results of the semi-automated annotation method openpose and the SAAnnot-C3Pap proposed in this paper. As a result of comparison, the proposed method showed improvement of posture information incorrectly collected through openpose.

• Journal of Korean Society of Forest Science
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• v.111 no.2
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• pp.242-250
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• 2022

Here we aimed to date the year and season of the resin collection from Korean red pines at Worak mountain and investigate the natural healing ability of the wounds using the tree-ring analysis technique. We determined the dating of the resin collection based on the synchronization between the ring-width time series from the wound surface of the experimental trees and the local master chronology, which is the mean time series from the sound surface on the opposite side of the wounds. For the dating of resin collection, we selected thirteen Korean red pines with resin wounds. For the investigation on the annual healing ability of the wounds, we sampled three dead trees out of 13 trees as disks. Through the comparison of the individual ring-width time series from the wounds with the local master chronology, it was verified that the resin collection was undertaken between the spring of 1962 and the autumn of 1975. The mean healing length of the wounds was 15.8 cm over the preceding 42 years, making their annual mean healing 0.38 cm. Through our study we successfully verified the healing ability of the wounded Korean red pines for the resin collection as well as the undocumented resin collection history.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.16 no.6
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• pp.454-464
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• 2023

This paper proposes a low-power 8-bit asynchronous SAR ADC with a sampling rate of 1 MS/s for sensor node applications. The ADC uses bootstrapped switches to improve linearity and applies a VCM-based CDAC switching technique to reduce the power consumption and area of the DAC. Conventional synchronous SAR ADCs that operate in synchronization with an external clock suffer from high power consumption due to the use of a clock faster than the sampling rate, which can be overcome by using an asynchronous SAR ADC structure that handles internal comparisons in an asynchronous manner. In addition, the SAR logic is designed using dynamic logic circuits to reduce the large digital power consumption that occurs in low resolution ADC designs. The proposed ADC was simulated in a 180-nm CMOS process, and at a 1.8 V supply voltage and a sampling rate of 1 MS/s, it consumed 46.06 𝜇W of power, achieved an SNDR of 49.76 dB and an ENOB of 7.9738 bits, and obtained a FoM of 183.2 fJ/conv-step. The simulated DNL and INL are +0.186/-0.157 LSB and +0.111/-0.169 LSB.