• Journal of Power Electronics
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• v.15 no.2
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• pp.497-503
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• 2015

This paper analyses the harmonic pollution to power grids caused by several high-power rectifiers, summarizes the requirements for rectifiers in suppressing grid-side current harmonics and optimizes a new-type of current source PWM rectifier with a hybrid switch. The rectifier with a hybrid switch boasts significant current characteristics and cost advantages in the high-power area. To further enhance the working frequency of the current source rectifier with a hybrid switch for suppressing grid-side harmonics and reducing the inductance size, this paper proposes an optimal control strategy based on space vector. It also verifies that the optimal control strategy based on space vector can reduce the total harmonic distortion of the grid-side current of the rectifier with a hybrid switch via circuit simulation and experimental results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1148-1159
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• 1997

In the broadband integrated service digital networks (B-ISDN), ATM switches hould be abld to accommodate diverse types of applications ith different traffic characteristics and quality ddo services (QOS). Thus, in order to increase the utilization of switches and satisfy the QOS's of each traffic type, some types of priority control schemes are needed in ATM switches. In this paper, a nonblocking input and output queueing ATm switch with capacity C is considered in which two classes of traffics with different loss probability constraints are admitted. 'Partial push-out' algorithm is suggested as a loss priority control schemes, and the performance of this algorithm is analyzed when this is adopted in input buffers of the switch. The quque length distribution of input buffers and loss probabilities of each traffic are obtained using a matrix-geometric solution method. Numerical analysis and simulation indicate that the utilization of the switch with partial push-out algorithm satisfying the QOS's of each traffic is much higher than that of the switch without control. Also, the required buffer size is reduced while satisfying the same QOS's.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2001.06a
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• pp.81-84
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• 2001

A signal path control switch has been designed and implemented with AT&T 0.5${\mu}{\textrm}{m}$ CMOS ORCA FPGA. This device controls the path of digital signals in SDH-based transmission system. The proposed switch is suitable for self-healing operation which protects against transmission network failure. The self-healing operation of the switch is effectively done by the reconfigurable information stored in the registers of the switch. This device consists of eight subparts such west-east transmitting parts, west-east receiving parts, add-drop control parts, AIS control Part, and CPU interface part. The device is capable to a ring network as well as a linear network.

• Proceedings of the KIPE Conference
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• 2013.11a
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• pp.133-134
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• 2013

현재 LS산전과 한국전력공사의 공동 개발을 통하여 60MW급 ${\pm}80kV$ 전류형 HVDC(High Voltage Direct Current) Transmission System 내 알고리즘 국산화 개발을 진행하고 있다. 제어 알고리즘 여러 레벨(AC Yard Control, Master Control, Pole Control, Phase Control)에서 운전하기 전 여러 고려사항 중 DC Yard 내 DC Switch의 투입/개방의 조건이 있다. 본 논문에서는 이러한 DC Line에 DC Switch의 상태를 효율적으로 제어하는 방법에 대해 소개하고자 한다.

• Journal of Electrical Engineering and information Science
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• v.2 no.6
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• pp.48-55
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• 1997

Advances in VLSI technology have brought us completely new design principles for the high-performance switching fabrics including ATM switches. From a practical point of view, port scalability of ATM switches emerges as an important issue while complexity and performance of the switches have been major issues in the switch design. In this paper, we propose a cost-effective approach to modular ATM switch design which provides the good scalability. Taking advantages of both time-division and space-division switch architectures, we propose a practically implementable large scale ATM switch architecture. We present a scalable shared buffer type switch for a building block and its expansion method. In our design, a large scale ATM switch is realized by interconnecting the proposed shared buffer switches in three stages. We also present an efficient control mechanism of the shared buffers, synchronization method for the switches in each stage, and a flow control between stages. It is believed that the proposed approach will have a significant impact on both improving the ATM switch performance and enhancing the scalability of the switch with a new cost-effective scheme for handling the traffic congestion. We show that the proposed ATM switch provides an excellent performance and that its cell delay characteristic is comparable to output queueing which provides the best performance in cell delay among known approaches.

• Proceedings of the KIEE Conference
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• 2001.07b
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• pp.1009-1011
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• 2001

This paper presents a new hybrid control scheme using Active-Clamped Class-E (ACCE) inverter of induction heating(IH) jar for high power applications. The proposed hybrid control scheme has characteristics, which act as class-E inverter at lower switch voltage and ACCE inverter at higher switch voltage than reference voltage of the main switch by feeding back voltage one as well as advantages of conventional ACCE inverter such as zero-voltage switching(ZVS) of the main switch and the reduced switch voltage due to the clamping circuit. Moreover, the proposed control method makes higher output power than conventional ACCE inverter control one since ACCE inverter is operated like class-E inverter at low voltage condition. The principle of the proposed control are explained in detail and the validity of the proposed control scheme is verified through the several interesting simulated and experimental results.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.53 no.6
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• pp.396-401
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• 2004

Single phase induction motor(SPIM) is one of the most widely used type of low power AC motors in the world, especially for domestic or commercial applications where a three phase power supply is not available. Single phase induction motors have no starting torque their own. So there are several ways of starting single phase induction motors. The most common type is the starting capacitor installed in series with the auxiliary winding to increase the starting torque. In the conventional systems, this function is conducted by a centrifugal switch. But the mechanical centrifugal switch has many problems such as switch malfunction. This paper presents the auxiliary winding control using digital universal starting switch to overcome these shortcomings of centrifugal switch.

• Journal of the Korea Computer Industry Society
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• v.2 no.4
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• pp.547-564
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• 2001

In this paper a simulation has been performed to compare and evaluate the performance between the EPRCA(Enhanced Proportional Rate Control Algorithm) and EMRCA(Explicit Max_min Rate Control Algorithm) switches. The variation of the ACR at the source end system, the queue length, the utilization rate of the link bandwidth and the share fairness at the transient and steady states are used as the evaluation criteria for the simulation. The EMRCA switch is more stable than the EPRCA switch and reduces its buffer size. Also, it achieves a higher utilization rate of the link bandwidth than the EPRCA switch. The hardware complexity of the EMRCA switch is significantly lower than the EPRCA and other rate-based switches. Since it eliminates the necessity of the floating-point operation for calculation of the MACR(Mean Allowed Cell Rate) at the switch.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.2
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• pp.338-343
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• 2010

Low cost motor drives are being sought for high volume energy efficient home appliances. Key to the realization of such low cost motor drives is to reduce the power electronic converter in terms of its components, particularly the active devices, finding the motor with least complexity for manufacturing and a controller that could extract the desired performance from the machine and converter combination. These and other factors such as self-starting, speed control over a wide range and most of all the crowning aspect of a four quadrant operation with bare minimum number of controllable switch (or switches) remain as formidable challenges for low cost motor drive realization. In this paper, a four quadrant switched reluctance motor (SRM) drive with only one controllable switch is realized by using a two-phase machine. The theory and operation of the proposed four-quadrant SRM drive with the proposed control algorithm for its realization are described. The motor drive is modeled, simulated and analyzed to verify its feasibility for self-starting, speed control and for four quadrant operation and the simulation results are presented. Experimental results confirm the validity of the proposed control algorithm for four quadrant control of the SRM drive. The focus of the paper is mainly directed toward the control algorithm for realizing the four-quadrant operation of the two-phase SRM drive with a single controllable switch converter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4B
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• pp.162-169
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• 2005

Network traffic measurements show that the data traffic on packet switched networks has the self-similar features which is different from the traditional traffic models such as Poisson distribution or Markovian process model. Most of the call admission control researches have been done on the performance analysis of a single network switch. It is necessary to consider the performance analysis of the proposed admission control scheme under interconnected switch environment because the data traffic transmits through switches in networks. From the simulation results, it is shown that the call admission control scheme may not operate properly on the interconnected switch even though the scheme works well on a single switch. In this parer, we analyze the cell loss probability, utilization and self-similarity of output ports of the interconnected networks switch by using shared buffer memory management schemes and propose the new call admission control scheme considering the interconnected network switches under self-similar traffic environments.