• Bulletin of the Korean Chemical Society
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• v.22 no.8
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• pp.903-908
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• 2001

The gene aeg-46.5, which is expressed under anaerobic condition, has putative triple -10 regions and four transcription start sites. The mRNA transcription level and its start point change depending on the aerobic/anaerobic growth condition. RNA polymerase and its regulatory proteins must choose which of three -10 region to use. The putative triple 10 region was mutated to make only one of them function with consensus -10 region sequence (TATAAT) and the other two as non-functional region. The results show that the second and third -10 regions are used for the aerobic/anaerobic expression. The third -10 region is responsible for the high aerobic to anaerobic switch ratio. This suggests that only the last two of the putative triple -10 region have functions on aeg-46.5 gene expression switch control. The phenotype of the mutated promoter was tested in the wild type cell and narL - cell. The results indicate that the control by NarL is independent from the selection of -10 region. The expression patterns on multi-copy plasmids and on single-copy chromosome were compared. These results show that the aerobic/anaerobic switch control of aeg-46.5 is through the choice of -10 region. The mechanism of choosing different -10 region remains to be seen.

• Progress in Superconductivity
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• v.5 no.1
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• pp.13-16
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• 2003

In this work, we have studied about an RSFQ (Rapid Single Flux Quantum) switch element. The circuit was designed, simulated, and laid out for mask fabrication. The switch cell was composed of a D flip-flop, a splitter, a confluence buffer, and a switch core. The switch core determined if the input data could pass to the output. “On” and o“off” controls in the switch core could be possible by utilizing an RS flip-flop. When a control pulse was input to the “on” port, the RS flip-flop was in the set state and passed the input pulses to the output port. When a pulse was input to the “off” port, the RS flip-flop was in the reset state and prevented the input pulses from transferring to the output port. We simulated and optimized the switch element circuit by using Xic, WRspice, and Julia. The minimum circuit margins in simulations were more than $\pm$20%. We also performed the mask layout of the circuit by using Xic and Lmeter.

• Korean Management Science Review
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• v.10 no.1
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• pp.139-156
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• 1993

Various ATM switches have been proposed since Asynchronous Transfer Mode (ATM) was recognized as appropriate for implementing broadband integrated services digital network (BISDN). An ATM switching network may be evaluated on two sides : traffic performances (maximum throughput, delay, and packet loss probability, etc.) and structural features (complexity, i.e. the number of switch elements necessary to construct the same size switching network, maintenance, modularity, and fault tolerance, etc.). ATM switching networks proposed to date tend to show the contrary characteristics between structural features and traffic performance. The Knockout Switch, which is well known as one of ATM switches, shows a good traffic performance but it needs so many switch elements and buffers. In this paper, we propose an input and output buffered Knockout Switch for the purpose of reducing the number of switch elements and buffers of the existing Knockout Switch. We analyze the traffic performance and the structural features of the proposed switching architecture through a discrete time Markov chain and compare with those of the existing Knockout Switch. It was found that the proposed architecture could reduce more than 40 percent of switch elements and more than 30 percent of buffers under a given requirement of cell loss probability of the switch.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.6
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• pp.1323-1333
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• 1997

In this paper, we propose an efficient architecture for a high-speed cell concentrator/distributor(HCCD) in an ATM(Asynchronous Transfer Mode) switch and by analyzeing the simulation results evaluate the performance of the proposed architecuture. The proposed HCCD distributes cells from a switch link to local processors, or concentrates cells from local processor s to a switch link. This design is to guarntee a high throughput for the IPC (inter-processor communication) link in a distributed ATM switching system. The HCCD is designed in a moudlar architecture to provide the extensibility and the flexibility. The main characteristics of the HCCD are 1) Adaption of a local CPU in HCCD for improving flexibility of the system, 2) A cell-baced statistical multiplexing function for efficient multiplexing, 3) A cell distribution function based on VPI(Virtual Path Identifier), 4) A bypassing capability for IPC between processor attached to the same HCCD, 5) A multicasting capability for point-to-multipoint communication, 6) A VPI table updating function for the efficient management of links, 7) A self-testing function for detecting system fault.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.3
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• pp.479-491
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• 1994

In this paper, we proposed cell priority control with 2-level thresholds, which was considered cell loss and cell delay requirement, in ATM switch with output buffer. Priority control mechanism presented in this paper improved cell loss rate for cell loss censitive cell and cell delay for delay censitive cell. In this mechanism cell loss rate and mean cell delay of cell priority control mechanism were obtained theoretically. The results show that cell loss rate and mean cell delay improvement become better by adjusting two thresholds according to QOS characteristics.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.5
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• pp.1384-1396
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• 1998

This paper ivestigates the performance of a relative rate (RR) switch algorithm for the rate-based available bit rate (ABR) flow control in asynchronous transfer mode (ATM) networks. A RR switch may notify the network congestion status to the source by suing the congestion indication (CI) bit or no increase (NI)bit in the backward RM (BRM) cells. A RR switch can be differently implemented according to the congestion detectio and notification methods. In this paper, we propose three implementation schemes for the RR switch with different congestion detection and notification methods, and analyze the allowed cell rate (ACR) of a source and the queue length of a switch in steady state. In addition, we derive the upper and lower bounds for the maximum and minimum queue lengths for each scheme respectively, and evaluate the effects of the ABR parameter values on the queue length. Furthermore, we suggest the range of the rage increase factor (RIF) and rate decrease factor (RDF) parameter values which can prevent buffer overflow and underflow at a switch.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.11C
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• pp.113-122
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• 2001

Several guidelines can be developed for a satellite-based ATM switch. One of the most important of these is that the switch must provide a requirement for CLRs on the order of 10-10 to meet the QoS of high- performance traffic and avoid costly retransmissions. In this paper, the proposed approach shows not only the better traffic performance but also requires the little switching elements and buffers compared with original Knockout switch and other scheduling algorithm. As a result, the complexity becomes reduced. Simulation results indicate that proposed approach shows excellent cell loss ratio compared with existing switch architecture. Also, iii performance can be approached to the cell loss ratio, which is requirement for the satellite system, as window size increases. An(1 it shows thats low complexity is induced. Therefore, the proposed approach is appropriate for satellite on-board ATM switch architecture.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.24 no.9
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• pp.62-70
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• 2010

Fuel cell system which can solve the environmental problem is receiving attention. To use utility power necessary power conversion system from low voltage that is generated by fuel cell system. because fuel cell has special characteristic of low voltage high current. To improve PCS's efficiency the paralleling method is used. Available the method could reduce the switching loss. But the existing research could not be found optimal result and accompanying several effects. In this study analysis several effects causing the parallel method. The effects have been demonstrated through simulations and experiments.

• Journal of Internet Computing and Services
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• v.9 no.2
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• pp.15-23
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• 2008

This paper proposes the new structural MOQ(Multiple Input/Output-Queued) switch which guarantees QoS while maintaining high efficiency and deals with the Anti-Empty algorithm which is new arbitration algorithm to be used for the proposed switch. The new structure of the proposed switch based on MIQ, MOQ is designed to have the same buffer speed as the external line speed. Also, the proposed switch makes it possible to remove the weak point of existing methods and introduces the new method of the MOQ operation to support QoS. Therefore, this switch is equal to the Output Queued switch in efficiency and delay, and guarantees the high-speed switching supporting QoS without cell loss.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.11
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• pp.2850-2861
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• 1996

This paper describes the design of AATM switch LIS of shared buffer type with linked-list architecture to control memory access. The proposed switch LSI consists of the buffer memory, controller and FIFO memory blocks and two special circuits to avoid the cell blocking. One of the special circuit is a new address control scheme with linked-list architecture which maintains the address of buffer memory serially ordered from write address to read address. All of the address is linked as chain is operated like a FIFO. The other is slip-flag register it will be hold the address chain when readaddress missed the reading of data. The circuits control the buffer memory efficiently and reduce the cell loss rate. As a result the designed chip operates at 33ns and occupied on 2.7*2.8mm$^{2}$ using 0.8.mu.m CMOS technology.