• Biomolecules & Therapeutics
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• v.27 no.6
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• pp.591-602
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• 2019

Human breast cancer cell line, MDA-MB-231, is highly invasive and aggressive, compared to less invasive cell line, MCF-7. To explore the genes that might influence the malignancy of MDA-MB-231, DNA microarray analysis was performed. The results showed that G0/G1 switch 2 (G0S2) was one of the most highly expressed genes among the genes upregulated in MDA-MB-231. Although G0S2 acts as a direct inhibitor of adipose triglyceride lipase, action of G0S2 in cancer progression is not yet understood. To investigate whether G0S2 affects invasiveness of MDA-MB-231 cells, G0S2 expression was inhibited using siRNA, which led to decreased cell proliferation, migration, and invasion of MDA-MB-231 cells. Consequently, G0S2 inhibition inactivated integrin-regulated FAK-Src signaling, which promoted Hippo signaling and inactivated ERK1/2 signaling. In addition, G0S2 downregulation decreased ${\beta}$-catenin expression, while E-cadherin expression was increased. It was demonstrated for the first time that G0S2 mediates the Hippo pathway and induces epithelial to mesenchymal transition (EMT). Taken together, our results suggest that G0S2 is a major factor contributing to cell survival and metastasis of MDA-MB-231 cells.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.1
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• pp.80-90
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• 1996

The efficienty of ATM is based on the statical multiplexing of fixed-length packets, which are called cells. The most important technical point for realizing ATM switching network is an arrangement of the buffers and switches. Current most ATM switching networks are being achieved by using the switching modules based on the unit switch of $8{\times}8$ 150Mb/s or $16{\times}16$ 150Mb/s, the unit switch of $32{\times}32$150Mb/s for a large scale system is under study in many countries. In this paper, we proposed a new $32{\times}32$(4.9Gb/s throughput) ATM switch using Shared buffer memory switch which provides superior traffic characteristics in the cell loss, delay and throughput performance and easy LSI(Large Scale Integrated circuit). We analytically estimated and simulated by computer the buffer size into it. We also proposed the configuration of the large capacity ATM switching network($M{\times}M$.M>1,000) consisting of multistage to improve the link speed by non-blocking.

• The Transactions of the Korea Information Processing Society
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• v.7 no.3
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• pp.923-934
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• 2000

• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.12
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• pp.9-24
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• 1995

In this paper, we proposed and analysed two kinds of priority control mechanism to archive the cell loss rate requirement and the delay requirement of each class. The service classes of our concern are the high time priority class(class 1) and the high loss priority class(class 2). Two kinds of priority control mechanism is divided by the method of storing the arriving class 2 cell in buffer on case of buffer full. The first one is the method which discarding the arriving class 2 cell, the second one is the mothod which storing the arriving class 2 cell on behalf of pushing out the class 1 cell in buffer. In the proposed priority schemes, one cell of the class 1 is transmitted whenever the maximum K cells of the class 2 is transmitted on case of transmitting the class 1 cell and the class 2 cell sequentially. In this paper, we analysed the cell loss rate and the mean cell delay for each class of the proposed priority scheme by using the Markov chain. The analytical results show that the characteristic of the mean cell delay becomes better for the class 1 cell and that of the cell loss rate becomes better for the class 2 cell by selecting properly the cell transfer ratio according to the condition of input traffic.

• The Transactions of the Korea Information Processing Society
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• v.5 no.6
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• pp.1610-1619
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• 1998

The ABR service class provides feedback based traffic control to transport bursty data traffic efficiently. Feedback based congestion control has first been studied to be applied to unicast connections. Recently. several congestion control algorithms for multicast connections have also been proposed as the number of ABR applications requiring multicast increases. With feedback based congestion control, the effectiveness of a traffic control scheme diminishes as propagation delay increases. Especially for a multicast connection, a remote destination may suffer unfair service compared to a local destination due to the delayed feedback. Amelioration of the disadvantages caused by feedback delay is therefore more important for remote destinations in multicast connections. This paper proposes a new switch behavior to provide effective feedback based mathc control for rentoh destinations. The proposed switches adjust the service rate dynamically in accordance woth the state of the downstream, that is, the congestion of the destinaion is immediately controlled by the nearest apstream switch before the source to ramp down the transmission rate of the connection. The proposed switch has an implementation overhead to have a separate buffer for each VC to adjust the service rate in accordance with a backward Rm cell of each VC. The buffer requirement id also increased at intermediate switches. Simulation results show that the proposed switch reduces the cell loss rate in both the local and the remote destinations and slso amelioratd the between the two destinations.

• The Transactions of the Korea Information Processing Society
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• v.6 no.1
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• pp.167-174
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• 1999

In this paper, we propose the adaptive separated-queueing ATM switching model for the effective processing of the various types of multimedia traffic by virtue of ATM switching network with multiple outlets which is the essential part of B-ISDN. This proposed model employs the dynamically separated buffering mechanism in the processing of two classes of cell, realtime service traffic and non-realtime service traffic, at the output buffer to enhance the overall QoS(Quality of Service). The adopted ATM switch architecture has Batcher-banyan based network, but it uses different topologies and control techniques 6to resolve the cell contention. For the performance evaluation of our proposed method, we have done both analytical modeling and simulation. The both results show that our proposed queueing strategy is quite appropriate to the ATM switch with multiple outlets and can quarantee the QoS requirements of the incoming multimedia traffic.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.8
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• pp.30-41
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• 2001

In this paper, the architecture of Dynamic GSMP V3(General Switch Management Protocol Version 3), an open interface protocol with resource management functions for efficient IP service on ATM over MPLS, is proposed and implemented in hardware. And we compare and analyze the proposed GSMP with the GSMP under standardization process in terms of CLR (Cell Loss Rate). We design the Slave block of the Dynamic GSMP V3 using SAM-SUNG SoG $0.5{\mu}m$ process, which performs functions for switch connection control in the ATM Switch. In order to compare difference performanaces between the proposed method and the conventional one, we conducts simulations using the minimum buffer search algorithm with random cell generation. The exponential results show that the proposed method leads to performance enhancement in CLR.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.863-866
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• 2003

Recently, there has been growing interests in the magneto-resistive random access memory (MRAM) because of its great potential as a future nonvolatile memory. In this paper, a CMOS macro-model for MRAM cell based on a twin cell structure is proposed. The READ and WRITE operations of the MTJ cell can be emulated by adopting data latch and switch blocks. The behavior of the circuit is confirmed by HSPICE simulations in a 0.35-${\mu}{\textrm}{m}$ CMOS process. We expect the macro model can be utilized to develope the core architecture and the peripheral circuitry. It can also be used for the characterization and the direction of the real MTJ cells.

• Journal of the Korean Operations Research and Management Science Society
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• v.21 no.3
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• pp.47-61
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• 1996

An ATM switch must deal with various kinds of input sources having different traffic characteristics and it must guarantee very small value of cel loss probability, about 10$^{8}$ -10$^{12}$ , to deal with loss-sensitive traffics. In order to estimate such a rate event probability with simulation procedure, a variance reduction technique is essential for obtaining an appropriate level of precision with reduced cost. In this paper, we propose a hybrid simulation technique to achieve reduction of variance of cell loss probability estimator, where hybrid means the combination of analytical method and simulation procedure. A discrete time queueing model with multiple input sources and a finite shared buffer is considered, where the arrival process at an input source and a finite shared buffer is considered, where the arrival process at an input source is governed by an Interrupted Bernoulli Process and the service rate is constant. We deal with heterogeneous input sources as well as homogeneous case. The performance of the proposed hybrid simulation estimator is compared with those of the raw simulation estimator and the importance sampling estimator in terms of variance reduction ratios.

• Journal of Power Electronics
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• v.5 no.2
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• pp.99-103
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• 2005

In this paper, a novel circuit topology of a three-winding coupling inductor-assisting a high-frequency PWM boost chopper type DC-DC power converter with a high boost voltage conversion ratio and low switch voltage stress is proposed for the new energy interfaced DC power conditioner in solar photovoltaic and fuel cell generation systems. The operating principle in a steady state is described by using its equivalent circuits under the practical condition of energy processing of a lossless capacitive snubber. The newly-proposed power MOSFET boost chopper type DC-DC power converter with the three-winding coupled inductor type transformer and a single lossless capacitor snubber is built and tested for an output power of 500W. Utilizing the lower voltage and internal resistance power MOSFET switch in the proposed PWM boost chopper type DC-DC power converter can reduce the conduction losses of the active power switch compared to the conventional model. Therefore, the total actual power conversion efficiency under a condition of the nominal rated output power is estimated to be 81.1 ％, which is 3.7％ higher than the conventional PWM boost chopper DC power conversion circuit topology.