• Journal of Semiconductor Engineering
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• 제1권2호
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• pp.74-80
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• 2020

Due to its superior error correcting performance with affordable hardware complexity, the Polar code becomes one of the most important error correction codes (ECCs) and now intensively examined to check its applicability in various fields. However, Successive Cancellation (SC) decoding that brings the advanced Successive Cancellation List (SCL) decoding suffers from the long latency due to the nature of serial processing limiting the practical implementation. To mitigate this problem, many decoding architectures, mainly divided into pruning and parallel decoding, are presented in previous manuscripts. In this paper, we compare the recent SC decoding architectures and analyze them using a tree structure.

• 전기전자학회논문지
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• 제24권2호
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• pp.550-558
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• 2020

Polar code의 복호 기법 중에 하나인 연속 제거 (successive cancellation; SC) 복호는 순차적으로 복호를 수행해야하는 특성으로 인해 지연시간이 길고, 복호를 위해 필요한 하드웨어 면적이 크다. 이를 극복하기 위하여 다수의 연구들이 진행되었으며, 본 논문에서는 연속 제거 복호를 기반으로 한 복호 기법을 가지치기 (pruning) 복호 기법들과 다중-경로 (multi-path) 복호기법들로 나누어 정리하였다. 가지치기 복호기법에는 SSC (simplified SC), fast-SSC, 신드롬 판단 기반 복호 등이 있으며, 다중-경로 복호 기법에는 2-비트 연속 제거 복호와 redundant-LLR 표현 기반의 복호가 있다. 본 논문에서는 SSC, fast-SSC, 신드롬 판단, 2-비트 연속 제거, 그리고 redundant-LLR 표현 기반의 복호 기법들을 지연시간과 하드웨어 면적 측면에서 비교했으며, 비교 결과 신드롬 판단 기반 복호기법이 지연시간이 가장 짧고, redundant-LLR 표현 기반의 복호가 하드웨어 면적이 가장 작은 복호 기법이다.

• Journal of Communications and Networks
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• 제5권2호
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• pp.116-123
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• 2003

In this paper, we address the problem of designing multirate codes for a multiple-input and multiple-output (MIMO) system by restricting the receiver to be a successive decoding and interference cancellation type, when each of the antennas is encoded independently. Furthermore, it is assumed that the receiver knows the instantaneous fading channel states but the transmitter does not have access to them. It is well known that, in theory, minimummean- square error (MMSE) based successive decoding of multiple access (in multi-user communications) and MIMO channels achieves the total channel capacity. However, for this scheme to perform optimally, the optimal rates of each antenna (per-antenna rates) must be known at the transmitter. We show that the optimal per-antenna rates at the transmitter can be estimated using only the statistical characteristics of the MIMO channel in time-varying Rayleigh MIMO channel environments. Based on the results, multirate codes are designed using punctured turbo codes for a horizontal codedMIMOsystem. Simulation results show performances within about one to two dBs of MIMO channel capacity.

• 대한전자공학회논문지TC
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• 제48권4호
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• pp.24-36
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• 2011

본 논문에서는 Arikan이 제안했던 극 부호의 부호화 및 복호화의 대수적 식을 개선하여 이진 이산 무기억 대칭 채널에서 연속 제거 복호 알고리즘을 이용한 극 부호의 채널의 합성과 분리를 확인했다. 이진 이산 무기억 대칭 채널 W에서 양극화 행렬 ${G_2}^{{\otimes}n}$을 통하여 블록 길이 $2^n$인 극 부호를 효과적으로 구성하여 정보 비트를 전송할 수 있다. 특히, $N{\geq}2$일 때, Arikan 부호의 복잡도 O($Nlog_2N$)이다. 극 부호가 향후 다중점 통신의 문제에 대한 하나의 대안이 될 수 있다는 것을 확인하였다.

• 한국통신학회논문지
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• 제25권11A호
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• pp.1652-1660
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• 2000

본 논문에서는 DS/CDMA (Direct Sequence/Code Division Multipe Access) 시스템에서 임시 판정 함수로서 연판정 함수와 경판정 함수를 적용한 파이프라인화된 직렬 간섭 제어 구조(PSIC, Pipelined Successive Interference Cancellation)의 성능을 수식적으로 분석하고, 모의 실험을 통하여 검증한다. PSIC 구조는 다단 직렬 간섭 제거 구조(MSIC, Multistage Successive Interference Cancellation)가 가지는 복호지연(decoding delay)의 문제를 해결하기 위해 파이프라인 구조를 MSIC에 적용한 것이다. 제안된PSIC 구조는 하드웨어의 복잡도(hardwar complexity)를 희생하여 비트 오율(BER, Bit Error Rate)의 증가 없이 MSIC에서 발생하는 복호 지연을 줄일 수 있다. 또한 제안된 PSIC 구조에서 연판정 함수와 경판정 함수를 각 간섭 제거 단(Cancellation stage)에서의 임시 판정 함수로 사용하여 얻게 되는 PSIC 구조들의 성능을 비교한다. 분석 및 실험 결과에 의하면 제안되 PSIC 구조에서는 경판정 함수를 사용할때의 성능이 연판정 함수를 사용할때의 성능보다 우수함을 알 수 있었다.

• International Journal of Internet, Broadcasting and Communication
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• 제12권4호
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• pp.18-25
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• 2020

In the fifth generation (5G) and beyond 5G (B5G) mobile communication, non-orthogonal multiple access (NOMA) has attracted great attention due to higher spectral efficiency and massive connectivity. We investigate the impacts of the channel estimation errors on the bit-error rate (BER) of NOMA, especially with the single-user decoding (SUD) receiver, which does not perform successive interference cancellation (SIC), in contrast to the conventional SIC NOMA scheme. First, an analytical expression of the BER for SUD NOMA with channel estimation errors is derived. Then, it is demonstrated that the BER performance degrades severely up to the power allocation less than about 20%. Additionally, we show that for the fixed power allocation of 10% in such power allocation range, the signal-to-noise (SNR) loss owing to channel estimation errors is about 5 dB. As a consequence, the channel estimation error should be considered for the design of the SUD NOMA scheme.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.427-435
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• 2015

This paper presents a high-throughput low-complexity decoder architecture and design technique to implement successive-cancellation (SC) polar decoding. A novel merged processing element with a one's complement scheme, a main frame with optimal internal word length, and optimized feedback part architecture are proposed. Generally, a polar decoder uses a two's complement scheme in merged processing elements, in which a conversion between two's complement and sign-magnitude requires an adder. However, the novel merged processing elements do not require an adder. Moreover, in order to reduce hardware complexity, optimized main frame and feedback part approaches are also presented. A (1024, 512) SC polar decoder was designed and implemented using 40-nm CMOS standard cell technology. Synthesis results show that the proposed SC polar decoder can lead to a 13% reduction in hardware complexity and a higher clock speed compared to conventional decoders.

• 전자공학회논문지
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• 제52권10호
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• pp.3-10
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• 2015

본 논문에서는 비대칭 Slepian-Wolf 부호화에 극부호를 적용하는 방법을 고려하며, 부호율 적응성을 갖도록 극부호를 설계하는 방법을 제시한다. 제안된 극부호 기반 분산 소스 부호화에 연속제거 리스트 복호 기법을 적용하는 경우에 Slepian-Wolf의 한계에 매우 근접함을 확인하였으며, 이는 기존의 저밀도 패리티 검사 부호를 이용한 구현보다 현저하게 향상된 것이다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권5호
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• pp.550-556
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• 2016

Polar codes are one of the most favorable capacity-achieving codes due to their simple structure and low decoding complexity. However, because of the disappointing decoding performance realized using conventional successive cancellation (SC) decoders, polar codes cannot be used directly in practical applications. In contrast to conventional SC decoders, list SC (SCL) decoders with large list sizes (e.g. 32) achieve performances very close to those of maximum-likelihood (ML) decoders. In SCL decoders with large list sizes, however, hardware increase is a severe problem because an SCL decoder with list size L consists of L copies of an SC decoder. In this paper, we present a low-area SCL decoder architecture that applies the proposed merged processing element-sharing (MPES) algorithm. A merged processing element (MPE) is the basic processing unit in SC decoders, and the required number of MPEs is L(N-1) in conventional SCL decoders. Using the proposed algorithm reduces the number of MPEs by about 70% compared with conventional SCL decoders when the list size is larger than 32.

• ETRI Journal
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• 제46권3호
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• pp.485-500
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• 2024

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10^-4 at 2.7 E_b/N_o (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.