• 반도체디스플레이기술학회지
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• 제10권4호
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• pp.113-118
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• 2011

According to the high accuracy of semiconductor equipments, PCB substrate with much thin thickness is required. However, it is very difficult to sustain the PCB substrate without deformation in case of horizontal installation, due to low bending stiffness. In this research, new PCB process equipment with vertical installation has been developed in order to solve the problem of PCB substrate damage during etching process. As the main parts of etching system on PCB substrate, PCB substrate and JIG are analyzed through finite element method and experimental test. Through the analysis results of stress state, we could find the optimal JIG design to make the damage as low as possible.

• Structural Engineering and Mechanics
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• 제74권2호
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• pp.215-225
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• 2020

Thin films easily wrinkle under compressive loading due to their small bending stiffness resulting from their tiny thickness. For a thin film deposited on a functionally graded substrate with non-uniform stiffness exponentially changes along the length span in this paper, the uniaxial wrinkling problem is solved analytically in terms of hyper-Bessel functions. For infinite, semi-infinite and finite length systems the wrinkling load and wrinkling wavenumber are determined and compared with those in literature. In comparison with a homogeneous substrate-bounded film in which the wrinkling pattern is uniform along the length span, for a functionally graded substrate-film system the wrinkles accumulate around the softer location of the functionally graded substrate. Therefore, the effective length of the film influenced by the wrinkles decreases, the amplitude of the wrinkles on softer regions of the functionally graded substrate grows and the wrinkling load of the functionally graded substrates with higher softening rate decreases more. The results of the current research are expected to be useful in science and technology of thin films and wrinkling of the structures especially living tissues.

• 마이크로전자및패키징학회지
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• 제28권4호
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• pp.31-39
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• 2021

본 논문에서는 FEM(유한요소법)을 사용하여 PoP (Package on Package)용 PCB를 unit(유닛)과 substrate(서브스트레이트)로 분리한 warpage 해석과 warpage에 미치는 층별 두께의 영향도 분석과 층별 두께 조건을 다구찌법에 의한 SN비(Signal-to-Noise ratio)로 분석하였다. 해석 결과에 의하면 유닛 PCB는 회로층의 영향이 대단히 높았는데 특히 외층의 영향도가 높았다. 반면에 서브스트레이트 PCB는 회로층의 영향도가 높았으나 유닛 PCB에 비해 상대적으로 낮았으며 오히려 솔더 레지스트의 영향도가 증가하였다. 따라서 유닛 PCB와 서브스트레이트 PCB를 동시에 고려하여 PoP PCB의 층별 구조는 외부와 내부 회로층은 두껍게, 윗면 솔더 레지스트는 얇게 설계하고 바닥면 솔더 레지스트의 두께를 5 ㎛와 25 ㎛ 사이의 두께를 선정하는 바람직하다.

• Advances in nano research
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• 제7권1호
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• pp.25-38
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• 2019

This research is aimed at studying the asymmetric thermal buckling of porous functionally graded (FG) annular nanoplates resting on an elastic substrate which are made of two different sets of porous distribution, based on nonlocal elasticity theory. Porosity-dependent properties of inhomogeneous nanoplates are supposed to vary through the thickness direction and are defined via a modified power law function in which the porosities with even and uneven type are approximated. In this model, three types of thermal loading, i.e., uniform temperature rise, linear temperature distribution and heat conduction across the thickness direction are considered. Based on Hamilton's principle and the adjacent equilibrium criterion, the stability equations of nanoporous annular plates on elastic substrate are obtained. Afterwards, an analytical solution procedure is established to achieve the critical buckling temperatures of annular nanoplates with porosities under different loading conditions. Detailed numerical studies are performed to demonstrate the influences of the porosity volume fraction, various thermal loading, material gradation, nonlocal parameter for higher modes, elastic substrate coefficients and geometrical dimensions on the critical buckling temperatures of a nanoporous annular plate. Also, it is discussed that because of present of thermal moment at the boundary conditions, porous nanoplate with simply supported boundary condition doesn't buckle.

• 한국전기전자재료학회논문지
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• 제36권5호
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• pp.500-504
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• 2023

In this study, the heteroepitaxial thin film growth of β-Ga₂O₃ was studied according to the position of the susceptor in mist-CVD. The position of the susceptor and substrate was moved step by step from the center of the hot zone to the inlet of mist in the range of 0~50 mm. It was confirmed that the average thickness increased to 292 nm (D1), 521 nm (D2), and 580 nm (D3) as the position of the susceptor moved away from the center of the hot zone region. The thickness of the lower region of the substrate is increased compared to the upper region. The surface roughness of the lower region of the substrate also increased because the nucleation density increased due to the increase in the lifetime of the mist droplets and the increased mist density. Therefore, thin film growth of β-Ga₂O₃ in mist-CVD is performed by appropriately adjusting the position of the susceptor (or substrate) in consideration of the mist velocity, evaporation amount, and temperature difference with the substrate, thereby determining the crystallinity of the thin film, the thickness distribution, and the thickness of the thin film. Therefore, these results can provide insights for optimizing the mist-CVD process and producing high-quality β-Ga₂O₃ thin films for various optical and electronic applications.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2005년도 International Meeting on Information Displayvol.I
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• pp.446-449
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• 2005

The alignment property of liquid crystals on the two-easy axes substrate is investigated. The two-easy axes substrate frustrates the orientation of the LCs next to the substrate, and hence influences the birefringence of the LC cell. Experimental findings reveal that the ratio of the rubbing strengths in the different rubbing directions and the cell thickness substantially influence the birefringence of the LC cell. The surface anchoring energetic competition between the different rubbing directions contributes to the observed results.

• 마이크로전자및패키징학회지
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• 제22권1호
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• pp.75-81
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• 2015

본 논문에서는 2개의 패시브 소자가 임베디드된 PoP(Package on Package)용 양면 기판의 휨을 감소시키기 위해 유한요소법을 이용한 수치해석과 파라메타 설계를 위한 다구찌법이 사용되었다. 양면 회로층 두께와 솔더 레지스트 두께가 4인자 3수준으로 설계되어 파라메타 영향도가 분석되었다. 또한, 유닛 영역의 솔더 레지스트가 제거하거나 도포된 모델의 휨을 해석하여 솔더 레지스트의 영향도를 분석하였다. 마지막으로 실험을 통해 수치해석과 다구찌법에 의한 파라메타 설계의 효과를 입증하였다. 연구결과에 의하면 휨에 미치는 영향은 볼 사이드에 있는 회로층이 지배적으로 크고 칩 사이드의 회로층이 두 번째로 크며 솔더 레지스트의 영향이 가장 작았다. 또한, 칩 사이드 유닛영역의 솔더 레지스트는 도포 유무에 따른 영향도가 매우 작았다. 한편 기판의 휨은 볼 사이드 회로층의 두께가 얇을수록, 칩 사이드 회로층의 두께와 솔더 레지스트의 두께는 두꺼울수록 감소하였다.

• 한국산업융합학회 논문집
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• 제23권6_2호
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• pp.1051-1058
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• 2020

The chemical mechanical planarization (CMP) is a process of physically and chemically polishing the semiconductor substrate. The planarization quality of a substrate can be evaluated by the within wafer non-uniformity (WIWNU). In order to improve WIWNU, it is important to manage the pad profile. In this study, a device capable of non-contact measurement of the pad thickness profile was developed. From the measured pad profile, the profile of the pad surface and the groove was extracted using the envelope function, and the pad thickness profile was derived using the difference between each profile. Thickness profiles of various CMP pads were measured using the developed PMS and envelope function. In the case of IC series pads, regardless of the pad wear amount, the envelopes closely follow the pad surface and grooves, making it easy to calculate the pad thickness profile. In the case of the H80 series pad, the pad thickness profile was easy to derive because the pad with a small wear amount did not reveal deep pores on the pad surface. However, the pad with a large wear amount make errors in the lower envelope profile, because there are pores deeper than the grooves. By removing these deep pores through filtering, the pad flatness could be clearly confirmed. Through the developed PMS and the pad thickness profile calculation method using the envelope function, the pad life, the amount of wear and the pad flatness can be easily derived and used for various pad analysis.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2015년도 제46회 하계학술대회
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• pp.1134-1135
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• 2015

In this paper, we reported fabrication of sealing the glass substrate using laser treatment at low temperature for electrochemical luminescence (ECL) cell. The laser treatment at temperature is using laser diode. The glass substrate sealing by laser treatment tested at 1-5 W, 1-5 mm/s for builted and tested. The sealing laser treatment method will allow associate coordination between the two glass substrate was enclosed. The effect of laser treatment to sealing the glass substrate was found to have cracks and air gap at best thickness of about $845-780{\mu}m$ for condition 5 W, 1-5 mm/s. The surface of sealing was roughness which was not influent to electrodes So, it is more effective viscosity between two glasses substrate.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2010년도 제39회 하계학술대회 초록집
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• pp.71-71
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• 2010

Copper oxide thin films were deposited on the p-type Si(100) by r.f. magnetron sputtering as a function of different substrate temperature. The deposited copper oxide thin films were investigated by atomic force microscopy (AFM), scanning electron microscopy (SEM), spectroscopic ellipsometry (SE), X-ray diffraction (XRD), and X-ray photoelectron spectroscopy (XPS). The SEM and SE data show that the thickness of the copper oxide films was about 170 nm. AFM images show that the surface roughness of copper oxide films was increased with increasing substrate temperature. As the substrate temperature increased, monoclinic CuO (111) peak appeared and the crystal size decreased while the monoclinic CuO (-111) peak was independent on the substrate temperature. The oxidation states of Cu 2p and O 1s resulted from XPS were not affected on the substrate temperature. The contact angle measurement was also studied and indicated that the surface of copper oxide thin films deposited high temperature has more hydrophobic surface than that of deposited at low temperature.