• 제목/요약/키워드: substrate layers

검색결과 1,026건 처리시간 0.036초

초고진공 전자공명 플라즈마를 이용한 SiC buffer layer 형성에 관한 연구 (A Study on SiC Buffer Layer Prepared by Ultra High Vacuum Electron Cyclotron Resonance CVD)

  • 전우곤;표재확;황기웅
    • 대한전기학회:학술대회논문집
    • /
    • 대한전기학회 1995년도 추계학술대회 논문집 학회본부
    • /
    • pp.326-328
    • /
    • 1995
  • SiC buffer layers were grown on Si(100) substrates by ultra-high-vacuum electron cryclotron resonance plasma (UHV ECR plasma) from $CH_4/H_2$ mixture at 700$^{\circ}C$. The electron densities and temperature were measured by single probe. The axial plasma potentials measured by emissive probe had the double layer structure at positive substrate bias. Piranha cleaning was carried out as ex-situ wet cleaning. Clean and smooth silicon surface were prepared by in-situ hydrogen plasma cleaning at 540$^{\circ}C$. A short exposure to hydrogen plasma transforms the Si surface from 1$\times$1 to 2$\times$1 reconstruction. It was monitored by reflection high energy electron diffraction (RHEED). The defect densities were analysed by the dilute Schimmel etching. The results showed that the substrate bias is important factor in hydrogen plasma cleaning. The low base pressure ($5\times10^{-10}$ torr) restrains the $SiO_2$ growth on silicon surface. The grown layers showed different characteristics at various substrate bias. RHEED and K-ray Photoelectron spectroscopy study showed that grown layer was SiC.

  • PDF

Sputter Seeding을 이용한 CVD Cu 박막의 비선택적 증착 및 기판의 영향 (The Blanket Deposition and the Sputter Seeding Effects on Substrates of the Chemically Vapor Deposited Cu Films)

  • 박종만;김석;최두진;고대홍
    • 한국세라믹학회지
    • /
    • 제35권8호
    • /
    • pp.827-835
    • /
    • 1998
  • Blanket Copper films were chemically vapor deposited on six kinds for substrates for scrutinizing the change of characteristics induced by the difference of substrates and seeding layers. Both TiN/Si and {{{{ { SiO}_{2 } }}/Si wafers were used as-recevied and with the Cu-seeding layers of 40${\AA}$ and 160${\AA}$ which were produced by sputtering The CVD processes were exectued at the deposition temperatures between 130$^{\circ}C$ and 260$^{\circ}C$ us-ing (hfc)Cu(VTMS) as a precursor. The deposition rate of 40$^{\circ}C$ Cu-seeded substrates was higher than that of other substrates and especially in seeded {{{{ { SiO}_{2 } }}/Si substrate because of the incubation period reducing in-duced by seeding layer at the same deposition time and temperature. The resistivity of 160${\AA}$ Cu seeded substrate was lower then that of 40 ${\AA}$ because the nucleation and growth behavior in Cu-island is different from the behavior in {{{{ { SiO}_{2 } }} substrate due to the dielectricity of {{{{ { SiO}_{2 } }}.

  • PDF

리플로우과정의 용융 거동에 미치는 전기주석 도금층의 결정 형상 및 구조의 영향 (Effects of morphology and structure of electrolytic tin coating layers on the flow melting behaviors during reflow treatment)

  • 김태엽;조준형;이재륭;배대철;홍기정
    • 한국표면공학회지
    • /
    • 제33권5호
    • /
    • pp.373-380
    • /
    • 2000
  • The flow melting behavior of the electrolytic tinplate during reflow treatment was investigated in terms of morphology and structure of coating layers which were electrodeposited with variation of electrolyte temperature. It was commonly found that the nucleation density of the electrodeposits showed little difference with the electrolyte temperature, and the growth of electrodeposited tin occurred along <100> direction of (002) plane. At low electrolyte temperature, the (002) plane of tin nucleated paralleling to the substrate and grew perpendicularly to the substrate, which rendered porous rod-like deposits. With increasing the temperature, the (002) plane nucleated declining $15^{\circ}$ to the substrate and also grew to the normal <100> direction, which enabled lateral growth of the tin crystals and rendered compact deposits. During reflow treatment, the matte deposit transformed to the reflowed state via transition regions consisted of contraction, island formation, and wetting . The matte deposits formed at low temperature exhibited wide transition regions because of poor thermal transfer between crystals due to their porous nature. While that formed at high temperature transformed very rapidly to the reflowed state by enhanced thermal transfer between the compact crystals.

  • PDF

Assessment Corrosion and Bioactive Behavior of Bioglass Coating on Co-Cr-Mo Alloy By Electrophoretic Deposition For Biomedical Applications

  • Areege K. Abed;Ali. M. Mustafa;Ali M. Resen
    • Corrosion Science and Technology
    • /
    • 제23권3호
    • /
    • pp.179-194
    • /
    • 2024
  • A layer-by-layer coating was produced using electrophoretic deposition for a HA/Al2O3 coating layer and a bioglass coating layer on Co-Cr-Mo alloy with a roughness of 0.5 ㎛ (400 emery paper SiC). The corrosion behaviour was analyzed by assessing the coating layers' exceptional corrosion resistance, which outperformed the substrate. Cr ion release test using AAS was carried out, indicating that factional graded coating inhibited ion release from the uncoated substrate to coated sample. The porosity was expressed as a percentage, representing the extent of imperfections on the surface of all coatings. These imperfections fell within an acceptable range of 1% to 3%. The roughness of the coated surface was measured using atomic force microscopy, which revealed an excellent roughness value of 3.32 nm. Tape test technique for adhesion revealed that the removal area of the substrate coating layer varied by 11.92%. X-ray diffraction analysis confirmed the presence of all coating material peaks and verified phases of the deposited coating layers. These findings provided evidence that the coating composition remains unaffected by the electrophoretic deposition process. The bioactivity was assessed by immersion in a simulated bodily fluid, which revealed the formation of HCA during a period of 5 days.

Sn계 무연 솔더에 관한 연구

  • 이창배;정승부;서창제
    • 한국마이크로전자및패키징학회:학술대회논문집
    • /
    • 한국마이크로전자및패키징학회 2001년도 추계 기술심포지움
    • /
    • pp.75-87
    • /
    • 2001
  • Three different kinds of substrate used in this study : bare Cu substrate, Ni-P/Cu substrate with a Ni-P layer thickness of $5\mu\textrm{m},$ and Au/Ni-P/Cu substrate with the Ni-P and Au layers of $0.15\mu\textrm{m}$ and $5\mu\textrm{m}$ thickness respectively. The wettability of various Sn-base solders was affected by the substrate metal finish used, i.e., nickel, gold and copper. On the Au/Ni-F/Cu substrate, Sn-base solders wet better than any of the other substrate metal finishes tested. The interfacial reaction between various substrate and Sn-base solder was investigated at $70^{\circ}C,$ $100^{\circ}C,$ $120^{\circ}C,$ $150^{\circ}C,$ $170^{\circ}C$ and $200^{\circ}C$ for reaction times ranging from 0 day to 60 day. Intermetallic phases was formed along a Sn-base solder/ various substrate interface during solid-state aging. The apparent activation energy for growth of Sn-Ag/Cu, Sn-Ag-Bi/Cu, and Sn-Bi/Cu couples were 65.4, 88.6, and 127.9 Kj/mol, respectively. After isothermal aging, the fracture surface shoved various characteristics depending on aging temperature and time, and the types of BGA pad.

  • PDF

Cu/Sn 비아를 적용한 일괄적층 방법에 의한 다층연성기판의 제조 (Fabrication of Laminated Multi-layer Flexible Substrate with Cu/Sn Via)

  • 이혁재;유진
    • 마이크로전자및패키징학회지
    • /
    • 제11권4호
    • /
    • pp.1-5
    • /
    • 2004
  • 다층 연성기판은 높은 전기 전도성과 낮은 절연상수로 잘 알려진 구리와 폴리이미드로 구성되어 있다. 본 연구에서는 이러한 다층연성기판을 패턴된 스테인리스 스틸 위에 구리선을 전기도금하고 폴리이미드를 코팅함에 의해서 균일한 형태의 $5{\mu}m$-pitch의 전도선을 제조하는데 성공하였다. 또한, 다층기판 형성시 비아흘은 UV 레이저로 형성시켰으며 구리와 주석을 전기 도금함으로 이를 채웠다. 그런다음 비아와 전도선이 붙은 채로 스테인리스 스틸에서 벗겨냈다. 이렇게 형성된 각각의 층을 한번에 적층하여 다층연성기판을 완성하였다. 적층시 주석과 구리사이에 고체상태 반응(Solid state reaction)이 발생하여 $Cu_6Sn_5$ and $Cu_3Sn$을 형성하였으며 비아패드에 비아가 수직으로 위치한 완전한 형태의 층간 연결을 형성하였다. 이러한 비아 형성 공정은 V형태의 비아나 페이스트 비아와 비교할 때 좋은 전기적 특성, 저가공정등의 여러 장점을 가지고 있다.

  • PDF

GaAs on Si substrate with dislocation filter layers for wafer-scale integration

  • Kim, HoSung;Kim, Tae-Soo;An, Shinmo;Kim, Duk-Jun;Kim, Kap Joong;Ko, Young-Ho;Ahn, Joon Tae;Han, Won Seok
    • ETRI Journal
    • /
    • 제43권5호
    • /
    • pp.909-915
    • /
    • 2021
  • GaAs on Si grown via metalorganic chemical vapor deposition is demonstrated using various Si substrate thicknesses and three types of dislocation filter layers (DFLs). The bowing was used to measure wafer-scale characteristics. The surface morphology and electron channeling contrast imaging (ECCI) were used to analyze the material quality of GaAs films. Only 3-㎛ bowing was observed using the 725-㎛-thick Si substrate. The bowing shows similar levels among the samples with DFLs, indicating that the Si substrate thickness mostly determines the bowing. According to the surface morphology and ECCI results, the compressive strained indium gallium arsenide/GaAs DFLs show an atomically flat surface with a root mean square value of 1.288 nm and minimum threading dislocation density (TDD) value of 2.4×107 cm-2. For lattice-matched DFLs, the indium gallium phosphide/GaAs DFLs are more effective in reducing the TDD than aluminum gallium arsenide/GaAs DFLs. Finally, we found that the strained DFLs can block propagate TDD effectively. The strained DFLs on the 725-㎛-thick Si substrate can be used for the large-scale integration of GaAs on Si with less bowing and low TDD.

유한요소해석에 의한 코팅면의 브리넬 경도 평가: 제3보 - 다층 코팅에 적용 (Evaluation of Brinell Hardness of Coated Surface Using Finite Element Analysis: Part 3 - Application to Multilayer Coatings)

  • 박태조;강정국
    • Tribology and Lubricants
    • /
    • 제37권6호
    • /
    • pp.240-245
    • /
    • 2021
  • Ceramic coatings with high hardness and excellent chemical stability have been successfully applied to various machine elements, tools, and implants. However, in the case of monolayer coating on soft substrates, a high-stress concentration at the interface between the coating and the substrate causes delamination of the coating layer. Recently, to overcome this problem, multilayer coatings with a metal layer with a low modulus of elasticity added between the ceramic and the substrate have been widely applied. This study presents the third part of a recent study and focuses on the effect of the number of coating layers on the Brinell hardness of multilayered coating with TiN/Ti, following the two previous studies on a new Brinell hardness test method for a coated surface and on the influence of substrate and coating thickness. Indentation analyses are performed using finite element analysis software, von Mises stress and equivalent plastic strain distributions, load-displacement curves, and residual indentation shapes are presented. The number of TiN/Ti layers considerably affect the stress distributions and indentation shapes. Moreover, the greater the number of TiN/Ti layers, the higher is the Brinell hardness. The stress and plastic strain distributions confirm that the multilayer coatings improve the wear resistance. The results are expected to be used to design and evaluate various coating systems, and additional study is required.