• 한국초전도학회:학술대회논문집
• /
• v.13
• /
• pp.21-21
• /
• 2003

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2009.06a
• /
• pp.335-336
• /
• 2009

• 한국초전도학회:학술대회논문집
• /
• 2009.07a
• /
• pp.56-56
• /
• 2009

• ETRI Journal
• /
• v.19 no.4
• /
• pp.402-413
• /
• 1997

A CMOS device which has an extended heavily-doped amorphous silicon source/drain layer on the field oxide and an amorphous silicon local interconnection (ASLI) layer in the self-aligned source/drain region has been studied. The ASLI layer has some important roles of the local interconnections from the extended source/drain to the bulk source/drain and the path of the dopant diffusion sources to the bulk. The junction depth and the area of the source/drain can be controlled easily by the ASLI layer thickness. The device in this paper not only has very small area of source/drain junctions, but has very shallow junction depths than those of the conventional CMOS device. An operating speed, however, is enhanced significantly compared with the conventional ones, because the junction capacitance of the source/drain is reduced remarkably due to the very small area of source/drain junctions. For a 71-stage unloaded CMOS ring oscillator, 128 ps/gate has been obtained at power supply voltage of 3.3V. Utilizing this proposed structure, a buried channel PMOS device for the deep submicron regime, known to be difficult to implement, can be fabricated easily.

• The Transactions of the Korean Institute of Electrical Engineers C
• /
• v.51 no.3
• /
• pp.134-140
• /
• 2002

Deep submicron NMOSFETs with elevated source/drain can be fabricated using self-aligned selective epitaxial growth(SEG) of silicon for enhanced device characteristics with shallow junction compared to conventional MOSFETs. Shallow junctions, especially with the heartily-doped S/D residing in the elevated layer, give hotter immunity to Yt roll off, drain-induced-barrier-lowering (DIBL), subthreshold swing (SS), punch-through, and hot carrier effects. In this paper, the characteristics of both deep submicron elevated source/drain NMOSFETs and conventional NMOSFETs were investigated by using TSUPREM-4 and MEDICI simulators, and then the results were compared. It was observed from the simulation results that deep submicron elevated S/D NMOSFETs having shallower junction depth resulted in reduced short channel effects, such as DIBL, SS, and hot carrier effects than conventional NMOSFETs. The saturation current, Idsat, of the elevated S/D NMOSFETs was higher than conventional NMOSFETs with identical device dimensions due to smaller sheet resistance in source/drain regions. However, the gate-to-drain capacitance increased in the elevated S/D MOSFETs compared with the conventional NMOSFETs because of increasing overlap area. Therefore, it is concluded that elevated S/D MOSFETs may result in better device characteristics including current drivability than conventional NMOSFETs, but there exists trade-off between device characteristics and fate-to-drain capacitance.

• Journal of the Korean Magnetics Society
• /
• v.15 no.2
• /
• pp.61-66
• /
• 2005

In order to make submicron cell for spin-injection device, lift-off method using Pt stencil and wet etching was chosen. This approach allows batch fabrication of stencil substrate with electron-beam lithography. It simplifies the process between magnetic film stack deposition and final device testing, thus enabling rapid turnaround in sample fabrication. Submicron junctions with size of $200nm{\times}300nm$ and $500nm{\times}500nm$ 500 nm and pseudo spin valve structure of $CoFe(30{\AA})/Cu(100{\AA})/CoFe(120{\AA}$) was deposited into the nanojunctions. MR ratio was 0.8 and $1.1{\%}$, respectively and spin transfer effect was confirmed with critical current of $7.65{\times}10^7A/cm^2$.

• 한국초전도학회:학술대회논문집
• /
• v.16
• /
• pp.48-48
• /
• 2006

• Vacuum Magazine
• /
• v.2 no.2
• /
• pp.17-23
• /
• 2015

Medium Energy Ion Scattering (MEIS) has been successfully used for ultrathin film analysis such as gate oxides and multilayers due to its single atomic depth resolution in compostional and structural depth profiling. Recently, we developed a time-of-flight (TOF) MEIS for the first time, which can analyze a $10{\mu}m$ small spot. Small spot analysis would be useful for test pattern analysis in semiconductor industry and various thin film technology. The ion beam damage problem is minimized due to its improved collection efficiency by orders of magnitude and the ion beam neutralization problem is removed completely for quantitative analysis. Newly developed TOF-MEIS has been applied for gate oxides, ultra shallow junctions, nanoparticles, FINFET structures to provide compositional and structural profiles. Further development for submicron spot analysis and applications for functional nano thin films and nanostructured materials are expected for various nanotechnology and biotehnology.

• Journal of the Korean Institute of Telematics and Electronics T
• /
• v.35T no.1
• /
• pp.7-13
• /
• 1998

The VLSI devices of submicron level trend to have a lowering of reliability because of hot carriers by two dimensional influences which are caused by short channel effects and which are not generated in a long channel devices. In order to minimize the two dimensional influences, much research has been made into various types of source/drain structures. MOS typed tunnel transistor with Schottky barrier junctions at source/drain, which has the advantages in fabrication process, downsizing and response speed, has been proposed. The experimental device was fabricated with p type silicon, and manifested the transistor action, showing the unsaturated output characteristics and the high transconductance comparing with that in field effect mode. The results of trial indicate for better performance as follows; high doped channel layer to lower the driving voltage, high resistivity substrate to reduce the leakage current from the substrate to drain.

• Journal of the Korean Institute of Telematics and Electronics D
• /
• v.36D no.5
• /
• pp.21-28
• /
• 1999

A new method of making high speed self-aligned ESD (Elevated Source/Drain) MOSFET is proposed. Different from the conventional LDD (Lightly-Doped Drain) structure, the proposed ESD structure needs only one ion implantation step for the source/drain junctions, and makes it possible to modify the depth of the recessed channel by use of dry etching process. This structure alleviates hot-carrier stress by use of removable nitride sidewall spacers. Furthermore, the inverted sidewall spacers are used as a self-aligning mask to solve the self-align problem. Simulation results show that the impact ionization rate ($I_{SUB}/I_{D}$) is reduced and DIBL (Drain Induced Barrier Lowering) characteristics are improved by proper design of the structure parameters such as channel depth and sidewall spacer width. In addition, the use of removable nitride sidewall spacers also enhances hot-carrier characteristics by reducing the peak lateral electric field in the channel.