• Journal of Power Electronics
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• 제17권6호
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• pp.1402-1412
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• 2017

This paper presents a new high step-up dc/dc converter for renewable energy systems in which a high voltage gain is provided by using a coupled inductor. The operation of the proposed converter is based on a charging capacitor with a single power switch in its structure. A passive clamp circuit composed of capacitors and diodes is employed in the proposed converter for lowering the voltage stress on the power switch as well as increasing the voltage gain of the converter. Since the voltage stress is low in the provided topology, a switch with a small ON-state resistance can be used. As a result, the losses are decreased and the efficiency is increased. The operating principle and steady-states analyses are discussed in detail. To confirm the viability and accurate performance of the proposed high step-up dc-dc converter, several simulation and experimental results obtained through PSCAD/EMTDC software and a built prototype are provided.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 제6회 학술대회 논문집 일렉트렛트 및 응용기술연구회
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• pp.9-12
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• 2004

In this study, we investigated about electrooptics characteristic of three kind of TN cell on the polyimide surface. Monodomain alignments of thermal stressed TN cell over temperature of liquid crystal isotropic phase were almost same that of no thermal stressed TN cells. However, the thermal stressed TN cell have many defects. Also, threshold voltage and response time of thermal stressed TN cells show same performances of no thermal stressed TN cells. There were little changes of value in these TN cells. However, transmittances of TN cells on the polyimide surface decrease with increasing thermal stress time. Finally, the residual DC voltage of the thermal stressed TN cell on the polyimide surface show decrease of characteristics as increasing thermal stress time. Therefore, thermal stability of TN cell was decreased by high thermal stress for the long times.

• Journal of Power Electronics
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• 제16권2호
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• pp.436-446
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• 2016

A novel step-up DC-DC converter with a switched-coupled-inductor-capacitor (SCIC) which successfully integrates three-winding coupled inductors and switched-capacitor techniques is proposed in this paper. The primary side of the coupled inductors for the SCIC is charged by the input source, and the capacitors are charged in parallel and discharged in series by the secondary windings of the coupled inductor to achieve a high step-up voltage gain with an appropriate duty ratio. In addition, the passive lossless clamped circuits recycle the leakage energy and reduce the voltage stress on the main switch effectively, and the reverse-recovery problem of the diodes is alleviated by the leakage inductor. Thus, the efficiency can be improved. The operating principle and steady-state analyses of the converter are discussed in detail. Finally, a prototype circuit at a 50 kHz switching frequency with a 20-V input voltage, a 200-V output voltage, and a 200-W output power is built in the laboratory to verify the performance of the proposed converter.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1992년도 하계학술대회 논문집 B
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• pp.1150-1153
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• 1992

A new soft-switching resonant type inverter is proposed to obtain the low voltage stress. In this proposed inverter, only one additional switch is used for the soft commutation. Therefore, a simple structure and a easy control can be available. Moreover, the PWM capability can be highly improved due to tile convenient choice of switching condition. Based on the operational principle, analysis and design procedures are described. Through the simulation, the operation of the proposed invertor is verified.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1101-1104
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• 2003

In this paper, we analyzed the gate current and substrate current by the hot carrier effects and restoration phenomenon of characteristics by time in the p-channel MOSFETs. The Stress voltage condition is a voltage in maximum gate current and time is 3s, 10s, 30s, l00s, 1000s, 2000s and 3000s. As results of analysis, the gate current and substrate current were decreased by stress time, and the restoration time of characteristics were shown the results that were decreased by the exponential times.

• 한국전기전자재료학회논문지
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• 제21권7호
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• pp.652-659
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• 2008

The nonlinear electrical properties and aging characteristics against surge stress of ZPCCL-based varistors were investigated for different sintering temperatures of the range $1240-1300^{\circ}C$. As the sintering temperature increased, the varistor voltage decreased from 732.2 to 53.8 V/mm, the nonlinear exponent decreased from 58.5 to 4.1, and the leakage current increased from $0.38{\mu}A$ to $46.5{\mu}A$. The varistors sintered at $1250^{\circ}C$ and $1260^{\circ}C$ exhibited the high stability against multiple surge, $150A/cm^2(8{\times}20{\mu}s)$. On the whole, the variation rate of electrical characteristics against impulse current stress was gradually increased in order of varistor voltage$\rightarrow$nonlinear exponent$\rightarrow$dissipation facto$\rightarrow$leakage current.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.719-722
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• 2003

This work investigates the device degradation p-channel PD SOI devices at various applied voltages as well as stress temperatures with respect to Body-Contact SOI (BC-SOI) and Floating-Body SOI (FB-SOI) MOSFETs. It is observed that the drain current degradation at the gate voltage of the maximum gate current is more significant in FB-SOI devices than in BC-SOI devices. For a stress at the gate voltage of the maximum gate current and elevated temperature, it is worth noting that the $V_{PT}$ Will be decreased by the amount of the HEIP plus the temperature effects. For a stress at $V_{GS}$ = $V_{DS}$ . the drain current decreases moderately with stress time at room temperature but it decreases significantly at the elevated temperature due to the negative bias temperature instability.

• Transactions on Electrical and Electronic Materials
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• 제18권1호
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• pp.51-54
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• 2017

TFTs (thin film transistors) were fabricated using a-SIZO (amorphous silicon-indium-zinc-oxide) channel by RF (radio frequency) magnetron sputtering at room temperature. We report the influence of various channel thickness on the electrical performances of a-SIZO TFTs and their stability, using TS (temperature stress) and NBTS (negative bias temperature stress). Channel thickness was controlled by changing the deposition time. As the channel thickness increased, the threshold voltage ($V_{TH}$) of a-SIZO changed to the negative direction, from 1.3 to -2.4 V. This is mainly due to the increase of carrier concentration. During TS and NBTS, the threshold voltage shift (${\Delta}V_{TH}$) increased steadily, with increasing channel thickness. These results can be explained by the total trap density ($N_T$) increase due to the increase of bulk trap density ($N_{Bulk}$) in a-SIZO channel layer.

• 한국전기전자재료학회논문지
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• 제11권10호
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• pp.842-848
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• 1998

The stability of paraseodymium-based zinc oxide varistor consisting of Zn-Pr-Co-Cr-Y oxide was investigated according to yttria additives under different stress conditons, such as 0.8V\ulcorner\ulcorner/373K/12h and 0.85V\ulcorner\ulcorner/393K/12h. Wholly, all varistor after the stress showed nearly symmetric and stable I-V characteristics. Particularly, in the case of 2.0mol% and 4.0mol% yttria-added varistor showing a good I-V characteristics, the varation rate of varistor voltage were less 1% and that of nonlinear coefficient were about degree of 5%, and what is remarkable, leakage current with increasing stress time during the applied stress was almost constant. It the light of these facts, it is estimated that varistor constituents having 2.0mol% and 4.0mol% yittria, respectively, will be utilized to various application fields.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2014년도 추계학술대회
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• pp.769-772
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• 2014

비정질 InGaZnO 박막트랜지스터의 Gate Overlap 길이에 따른 NBS(Negative Bias Stress) 및 hot carrier 스트레스 후 시간별 문턱전압의 변화에 의한 소자신뢰도를 분석하였다. 측정에 사용된 소자는 비정질 InGaZnO TFT이며 채널 폭 $W=104{\mu}m$, 게이트 길이 $L=10{\mu}m$이며 Gate Overlap 길이는 $0,1,2,3{\mu}m$를 사용하였다. 소자 신뢰도는 전류-전압을 측정하여 분석하였다. 측정 결과, hot carrier 스트레스 후 Gate Overlap 길이가 증가할수록 문턱전압의 변화가 증가하였다. 또한, NBS 후에는 Gate Overlap 길이가 증가할수록 문턱전압의 변화가 감소하였고 장시간 스트레스 후에 hump가 발생하였다.