• Title/Summary/Keyword: stereoscopic hardware architecture

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Depth-adaptive Sharpness Adjustments for Stereoscopic Perception Improvement and Hardware Implementation

  • Kim, Hak Gu;Kang, Jin Ku;Song, Byung Cheol
    • IEIE Transactions on Smart Processing and Computing
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    • v.3 no.3
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    • pp.110-117
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    • 2014
  • This paper reports a depth-adaptive sharpness adjustment algorithm for stereoscopic perception improvement, and presents its field-programmable gate array (FPGA) implementation results. The first step of the proposed algorithm was to estimate the depth information of an input stereo video on a block basis. Second, the objects in the input video were segmented according to their depths. Third, the sharpness of the foreground objects was enhanced and that of the background was maintained or weakened. This paper proposes a new sharpness enhancement algorithm to suppress visually annoying artifacts, such as jagging and halos. The simulation results show that the proposed algorithm can improve stereoscopic perception without intentional depth adjustments. In addition, the hardware architecture of the proposed algorithm was designed and implemented on a general-purpose FPGA board. Real-time processing for full high-definition stereo videos was accomplished using 30,278 look-up tables, 24,553 registers, and 1,794,297 bits of memory at an operating frequency of 200MHz.

A Real-Time Virtual Re-Convergence Hardware Platform

  • Kim, Jae-Gon;Kim, Jong-Hak;Ham, Hun-Ho;Kim, Jueng-Hun;Park, Chan-Oh;Park, Soon-Suk;Cho, Jun-Dong
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.12 no.2
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    • pp.127-138
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    • 2012
  • In this paper, we propose a real-time virtual re-convergence hardware platform especially to reduce the visual fatigue caused by stereoscopy. Our unique idea to reduce visual fatigue is to utilize the virtual re-convergence based on the optimized disparity-map that contains more depth information in the negative disparity area than in the positive area. Our virtual re-convergence hardware platform, which consists of image rectification, disparity estimation, depth post-processing, and virtual view control, is realized in real time with 60 fps on a single Xilinx Virtex-5 FPGA chip.