• Title/Summary/Keyword: squaring

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Time Discretization of the Nonlinear System with Variable Time-delayed Input using a Taylor Series Expansion

  • Choi, Hyung-Jo;Chong, Kil-To
    • 제어로봇시스템학회:학술대회논문집
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    • 2005.06a
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    • pp.2562-2567
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    • 2005
  • This paper suggests a new method discretization of nonlinear system using Taylor series expansion and zero-order hold assumption. This method is applied into the sampled-data representation of a nonlinear system with input time delay. Additionally, the delayed input is time varying and its amplitude is bounded. The maximum time-delayed input is assumed to be two sampling periods. Them mathematical expressions of the discretization method are presented and the ability of the algorithm is tested for some of the examples. And 'hybrid' discretization scheme that result from a combination of the ‘scaling and squaring' technique with the Taylor method are also proposed, especially under condition of very low sampling rates. The computer simulation proves the proposed algorithm discretized the nonlinear system with the variable time-delayed input accurately.

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Optimum BPF Bandwidth of Noncoherent Tau-Dither Loops for PN Code Tracking (PN부호의 동기추적을 위한 비코히어런트 TDL에서 최적의 BPF 대역폭)

  • 송문규;최흥택;차균현
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.19 no.8
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    • pp.1421-1432
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    • 1994
  • The optimum design and performance of noncoherent TDL considering the effect of distortions due to the IF bandpasss filters are described. NRZ data and ideal filter is presumed in the simulation. The optimum filter bandwidth is calculated in the sense of minimizing the loop's squaring loss, which is equivalent to minimizing the loop's tracking jitter for a given data rate and data signal-to-noise ratio. As a result, the optimum filter bandwidth depends on the signal-to-noise ratio, and is obtained in the range of about 1-2 times of the data rate.

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Compact implementations of Curve Ed448 on low-end IoT platforms

  • Seo, Hwajeong
    • ETRI Journal
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    • v.41 no.6
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    • pp.863-872
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    • 2019
  • Elliptic curve cryptography is a relatively lightweight public-key cryptography method for key generation and digital signature verification. Some lightweight curves (eg, Curve25519 and Curve Ed448) have been adopted by upcoming Transport Layer Security 1.3 (TLS 1.3) to replace the standardized NIST curves. However, the efficient implementation of Curve Ed448 on Internet of Things (IoT) devices remains underexplored. This study is focused on the optimization of the Curve Ed448 implementation on low-end IoT processors (ie, 8-bit AVR and 16-bit MSP processors). In particular, the three-level and two-level subtractive Karatsuba algorithms are adopted for multi-precision multiplication on AVR and MSP processors, respectively, and two-level Karatsuba routines are employed for multi-precision squaring. For modular reduction and finite field inversion, fast reduction and Fermat-based inversion operations are used to mitigate side-channel vulnerabilities. The scalar multiplication operation using the Montgomery ladder algorithm requires only 103 and 73 M clock cycles on AVR and MSP processors.

A Novel GPS Initial Synchronization Scheme with Decomposed Differential Matched Filter (분해형 차분 정합필터를 갖는 새로운 GPS 초기동기 방식)

  • Park, Sang-Hyun;Lee, Sang-Jeong
    • Journal of Institute of Control, Robotics and Systems
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    • v.8 no.2
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    • pp.185-192
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    • 2002
  • A novel GPS initial synchronization scheme with low hardware complexity is proposed. The proposed method has the decomposed differential matched filter, which consists of 25% multiplier and adder of the conventional matched filter. This paper presents the generalized mean acquisition time of initial synchronization scheme with multiple correlator. It is shown that the proposed method, in spite of its low hardware complexity, has the equal performance to the conventional method. The performance of the proposed method is verified through the simulation test by the GPS simulator. It is shown that the proposed method prevents the squaring loss of non-coherent integration.

Robust Controller Design for Non-square Linear Systems Using a Passivation Approach (수동화 기법에 의한 비정방 선형 시스템의 강인 제어기 설계)

  • 손영익
    • Journal of Institute of Control, Robotics and Systems
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    • v.8 no.11
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    • pp.907-915
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    • 2002
  • We present a state-space approach to design a passivity-based dynamic output feedback control of a finite collection of non-square linear systems. We first determine a squaring gain matrix and an additional dynamics that is connected to the systems in a feedforward way, then a static passivating (i.e. rendering passive) control law is designed. Consequently, the actual feedback controller will be the static control law combined with the feedforward dynamics. A necessary and sufficient condition for the existence of the parallel feedfornward compensator (PFC) is given by the static output feedback fomulation, which enables to utilize linear matrix inequality (LMI). The effectiveness of the proposed method is illustrated by some examples including the systems which can be stabilized by the proprotional-derivative (PD) control law.

Modification of IEC Flickermeter to Measure the Flicker Caused by Inter-Harmonics (상호고조파에 의한 플리커의 측정에 가능한 IEC 플리커미터의 설계)

  • Cho, Soo-Hwan;Jung, Jae-Ahn;Jang, Gil-Soo;Kwon, Sae-Hyuk
    • Proceedings of the KIEE Conference
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    • 2007.07a
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    • pp.69-70
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    • 2007
  • Now the IEC flicker measuring algorithms and its flicker index of $P_{st}$ and $P_{lt}$ are accepted internationally as standards. But it is recently found that IEC flickermeter has a main drawback that it cannot afford to detect the fluctuating patterns of voltage envelope caused by interharmonics higher than 102Hz in the 60Hz power system. This is brought about by two components of IEC flicker measuring steps, squaring and low-pass filtering. This paper presents the innate defect of IEC flickermeter and proposes a modified measuring method considering the voltage flickers by subharmonics and interharmonics.

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Performance Analysis of AJ and LPI in Chirp Modulation System (Chirp 방식의 LPI 및 AJ 성능 분석)

  • 유흥균
    • Journal of the Korea Institute of Military Science and Technology
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    • v.5 no.1
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    • pp.119-126
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    • 2002
  • 본 논문에서는 chirp 변조를 이용한 통신 시스템의 LPI(low probability of intercept)와 AJ(anti-jamming)성능을 분석하였다. 인터셉터에 DAM(delay and multiplier)과 SC(squaring circuit)가 이용된 경우 CBPSK(Chirped BPSK)의 LPI 성능을 분석하였다. 스펙트럼 확산 방식의 CBPSK와 DS/BPSK 시스템에 대한 AJ 성능을 비교 분석 및 주파수 호핑 방식의 FH/CBFSK(Chirped BFSK)와 FH/BFSK, 그리고 FH/BCM(Binary Chirp Modulation) 시스템에 대한 AJ 성능을 분석하였다. LPI 결과로, CBPSK(Chirped BPSK)은 chirp 변수인 chirp 주기($T_3$가 커질수록 좋은 LPI 성능을 보인다. AJ 결과로, PBNJ(partial band noise jammer)환경에서 CBPSK 방식이 DS/BPSK 방식에 비하여 AJ 성능이 우수하고, 마찬가지로 FH/CBFSK 방식이 FH/BFSK 방식에 비하여 AJ 성능이 우수함을 시뮬레이션으로 확인하였다.

Squaring the Circle in Perspective (방원도의 투영)

  • Kim, Hong-Jong
    • Journal for History of Mathematics
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    • v.27 no.6
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    • pp.395-402
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    • 2014
  • When the circle inscribed in a square is projected to a picture plane, one sees, in general, an ellipse in a convex quadrilateral. This ellipse is poorly described in the works of Alberti and Durer. There are one parameter family of ellipses inscribed in a convex quadrilateral. Among them only one ellipse is the perspective image of the circle inscribed in the square. We call this ellipse "the projected ellipse." One can easily find the four tangential points of the projected ellipse and the quadrilateral. Then we show how to find the center of the projected ellipse. Finally, we describe a pair of conjugate vectors for the projected ellipse, which finishes the construction of the desired ellipse. Using this algorithm, one can draw the perspective image of the squared-circle tiling.

Ankylosing Spondylitis Associated with Bilateral TMJ Ankylosis (강직성 척추염에 수반된 양측성 측두하악관절 강직)

  • Song Ju-Seop;Koh Kwang-Joon
    • Imaging Science in Dentistry
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    • v.30 no.3
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    • pp.217-222
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    • 2000
  • A 31-year-old male with the complaint of severe limitation of mouth opening was referred to our department of Chonbuk National University Hospital. The physical status of the patient was hyposthenic. Extraoral examination showed no condylar movement of the both temporomandibular joints, no pain, no facial swelling or paresthesia. Intraoral examination showed several cervical caries on the upper anterior teeth, and gingival swelling on the whole dentition. Transcranial view showed no condylar movement, and narrowing of joint spaces. Chest P-A view showed straightening of thoracic, lumbar spine, and squaring of vertebrae of the same spines. Conventional lateral radiograph of cervical spine showed calcification of the intervertebral ligament. Computed tomograph showed extensive bone formation between temporal bone and the condylar head at both sides. Laboratory findings showed positive reaction on HLA-B27 histocompatibility antigen and increased level of IgA, IgG, ESR. Based on the clinical, radiographic, and the laboratary findings, final diagnosis was made as bony ankylosis of the both temporomandibular joints secondary to ankylosing spondylitis.

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Design of Linear Systolic Arrays of Modular Multiplier for the Fast Modular Exponentiation (고속 모듈러 지수연산을 위한 모듈러 곱셈기의 선형 시스톨릭 어레이 설계)

  • Lee, Geon-Jik;Heo, Yeong-Jun;Yu, Gi-Yeong
    • Journal of KIISE:Computer Systems and Theory
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    • v.26 no.9
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    • pp.1055-1063
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    • 1999
  • 공개키 암호화 시스템에서 주된 연산은 512비트 이상의 큰 수에 의한 모듈러 지수 연산으로 표현되며, 이 연산은 내부적으로 모듈러 곱셈을 반복적으로 수행함으로써 계산된다. 본 논문에서는 Montgomery 알고리즘을 분석하여 right-to-left 방식의 모듈러 지수 연산에서 공통으로 계산 가능한 부분을 이용하여 모듈러 제곱과 모듈러 곱셈을 동시에 수행하는 선형 시스톨릭 어레이를 설계한다. 설계된 시스톨릭 어레이는 VLSI 칩과 같은 하드웨어로 구현함으로써 IC 카드나 smart 카드에 이용될 수 있다.Abstract The main operation of the public-key cryptographic system is represented the modular exponentiation containing 512 or more bits and computed by performing the repetitive modular multiplications. In this paper, we analyze Montgomery algorithm and design the linear systolic array for performing modular multiplication and modular squaring simultaneously using the computable part in common in right-to-left modular exponentiation. The systolic array presented in this paper could be designed on VLSI hardware and used in IC and smart card.