• The Transactions of the Korea Information Processing Society
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• v.2 no.5
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• pp.757-767
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• 1995

In this paper, we present MI-MESI write-invalidate snooping cache coherence protocol which addresses several significant drawbacks of MESI and MI-MESI write -invalidate snooping cache coherence protocols under the split transaction bus based multiprocessor environment. In this protocol, each cache block maintains one of six cache states which represent Modified-shared, Invalid-by-other, Modified, Exclusive, Shared and Invalid states. By using these cache states, our protocol reduces both the access contention and unnecessary updates for the memory modules significantly, and thus providing the fast memory access time.

• Proceedings of the IEEK Conference
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• summer
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• pp.204-208
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• 2004

Embedded business will be expanded market more and more since customers seek more wearable and ubiquitous systems. Cellular telephones, PDAs, notebooks and portable multimedia devices could bring higher microprocessor revenues and more rewarding improvements in performance and functions. Increasing battery capacity is still creeping along the roadmap. Until a small practical fuel cell becomes available, microprocessor developers must come up with power-reduction methods. According to MPR 2003, the instruction and data caches of ARM920T processor consume $44\%$ of total processor power. The rest of it is split into the power consumptions of the integer core, memory management units, bus interface unit and other essential CPU circuitry. And the relationships among CPU, peripherals and caches may change in the future. The processor working on higher operating frequency will exact larger cache RAM and consume more energy. In this paper, we propose advanced low power trace cache which caches traces of the dynamic instruction stream, and reduces cache access times. And we evaluate the performance of the trace cache and estimate the power of the trace cache, which is compared with conventional cache.

• International Journal of Contents
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• v.3 no.1
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• pp.19-23
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• 2007

Recently, several main-memory index structures have been proposed to reduce the impact of secondary cache misses. In mainmemory storage systems, secondary cache misses have a substantial effect on the performance of index structures. However, recent studies still stiffer from secondary cache misses when visiting each level of index tree. In this paper, we propose a new index structure that minimizes the total amount of cache miss latency. The proposed index structure prefetched grandchildren of a current node. The basic structure of the proposed index structure is based on that of the CSB+-Tree, which uses the concept of a node group to increase fan-out. However, the insert algorithm of the proposed index structure significantly reduces the cost of a split. The superiority of our algorithm is shown through performance evaluation.

• The KIPS Transactions:PartA
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• v.13A no.2 s.99
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• pp.101-110
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• 2006

One of the most effective ways to improve cache performance is to exploit both temporal and spatial locality given by any program executional characteristics. This paper proposes a data cache with small space for low power but high performance on multimedia applications. The basic architecture is a split-cache consisting of a direct-mapped cache with small block sire and a fully-associative buffer with large block size. To overcome the disadvantage of small cache space, two mechanisms are enhanced by considering operational behaviors of multimedia applications: an adaptive multi-block prefetching to initiate various fetch sizes and an efficient block filtering to remove rarely reused data. The simulations on MediaBench show that the proposed 5KB-cache can provide equivalent performance and reduce energy consumption up to 40% as compared with 16KB 4-way set associative cache.

• Journal of Industrial Convergence
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• v.18 no.2
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• pp.69-75
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• 2020

Industrial IoT has much interested in wireless mesh networks (WMNs) due to cost effectiveness and coverage. According to the advance in caching technology, WMNs have been researched to overcome the throughput degradation of multihop environment. However, there is few researches of cache power consumption models for WMNs. In particular, a wired line based cache power consumption model in content-centric networks is not still proper to WMNs. In this paper, we split the amount of cache power from the idle power consumption of CPU, and then the cache hit ratio proportional power consumption model (CHR-model) is proposed. The proposed CHR-model provides more accurate power consumption in WMNs, compared with the conventional cache power efficiency based consumption model (CPE-model). The proposed CHR-model can provide a reference model to improve energy-efficient cache operation for Industrial IoT.

• Journal of Korea Game Society
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• v.8 no.2
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• pp.57-68
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• 2008

Texture Mapping is a technique for adding realism to an image in 3D graphics Chip. Bilinear filtering mode of this technique needs accesses of 4 texels to process one pixel. In this paper we analyzed the access pattern of texture, and proposed the high performance texture cache which can access 4 texels simultaneously. We evaluated using simulation results of 3D game(Quake 3, Unreal Tournament 2004). Simulation results show that proposed texture cache has high performance on the case where physical size is less then or equal 8KBytes.

• Journal of Internet Computing and Services
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• v.4 no.6
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• pp.75-86
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• 2003

In main-memory resident index structures, secondary cache misses considerably have an effect on the performance of index structures. Recently, several main-memory resident index structures that consider cache have been proposed to reduce the impact of secondary cache misses. However they still suffer from full secondary cache misses whenever visiting each level of a index tree, In this paper, we propose a new index structure that eliminates cache misses even when visiting each level of index tree. The proposed index structure prefetches the grandchildren of a current node. The basic structure of the proposed index structure is from CSB+-tree that uses the concepts of the node group to increase fan-out. However the insert algorithm of the proposed index structure reduces the cost of a split significantly, Also, we show the superiority of our algorithm through various performance evaluation.

• Journal of KIISE:Databases
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• v.31 no.6
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• pp.675-683
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• 2004

In main-memory resident index structures, secondary cache misses considerably have an effect on the performance of index structures. Recently, several main-memory resident index structures that consider cache have been proposed to reduce the impact of secondary cache misses. However they still suffer from full secondary cache misses whenever visiting each level of a index tree. In this paper, we propose a new index structure that eliminates cache misses even when visiting each level of index tree. The proposed index structure prefetches the grandchildren of a current node. The basic structure of the proposed index structure is from CSB+-tree that uses the concepts of the node group to increase fan-out. However the insert algorithm of the proposed index structure reduces the cost of a split significantly. Also, we show the superiority of our algorithm through various performance evaluation.

• Journal of Korea Spatial Information System Society
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• v.6 no.1 s.11
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• pp.19-29
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• 2004

Recently, studies have been performed to improve the cache performance of the R-Tree in main memory. A general mothed to improve the cache performance of the R-Tree is to reduce size of an entry so that a node can store more entries and fanout of it can increase. However, this method generally requites additional process to reduce information of entries and do not support incremental updates. In addition, the cache miss always occurs on moving between a parent node and a child node. To solve these problems efficiently, this paper proposes and evaluates the PR-Tree that is an extended R-Tree indexing method using prefetching in main memory. The PR-Tree can produce a wider node to optimize prefetching without additional modifications on the R-Tree. Moreover, the PR-Tree reduces cache miss rates that occur in moving between a parent node and a child node. In our simulation, the search performance, the update performance, and the node split performance of the PR-Tree improve up to 38%. 30%, and 67% respectively, compared with the original R-Tree.

• Journal of KIISE:Databases
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• v.30 no.4
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• pp.408-419
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• 2003

Data warehouses are usually dedicated to the processing of quires issued by decision support system(DSS). The response time of DSS queries is typically several orders of magnitude higher than the one of OLTP queries. Since DSS queries are often submitted interactively, techniques for reducing their response time are important. The caching of query results is one such technique particularly well suited to the DSS environment. In this paper, we present a cache manager for such an environment. Specifically, we define a canonical form of query. The cache manager looks up a query based on the exact query match or using a suggested query split process if the query is found is non-canonical form or in canonical form, respectively. It dynamically maintains the cache content by employing a profit function which reflects in an integrated manner the query execution cost, the size of query result, the reference rate, the maintenance cost of each result due to updates of their base tables, and the frequency of such updates. We performed the experimental evaluation and it positively shows the performance benefit of our cache manager.