• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1999.11a
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• pp.290-293
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• 1999

(Ba$_{0.5}$Sr$_{0.5}$)TiO$_3$ thin films were fabricated at different RTA temperatures and thicknesses by Sol-Gel method. Solution consisting of acetate powders and titanium isopropoxide in a mixture of acetic acid and ethylene glycol were spin coated onto Pt/Ti/SiO$_2$/Si substrates. The films were annealed in the temperature range of 650~80$0^{\circ}C$ for 3 minutes by rapid thermal annealing. These BST thin films were fully crystallized at 75$0^{\circ}C$ and showed a maximum dielectric constant value of $\varepsilon$$_{r}$=~468 and dielectric loss was ~0.025 at a thickness of approximately 4000$\AA$.EX>.>.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.05b
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• pp.42-45
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• 2001

The high permittivity are applied to DRAM and FRAM. (Ba,Sr)$TiO_3$ (EST) thin films were prepared by Sol-Gel method. BST solution was made and spin-coated on $Pt/SiO_2/Si$ substrate at 4000 [rpm] for 10 seconds in a time coating. Coated specimens were dried at $90[^{\circ}C]$ for 5 minutes. Coating process was repeated from 3 times to 5 times and then sintered at $750[^{\circ}C]$ for 30 minutes. Each specimen was analyzed structure and electrical characteristics. Thickness of BST ceramics thin films are about 2600-2800[$\AA$] in 3 times. Dielectric constant of thin films was little decreased at 1[KHz]~1[MHz]. Dielectric constant and loss to frequency were 250 and 0.02 in BST3. The property of leakage current was stable When the applied voltage was 0~3[V] Leakage current was $10^{9}\sim10^{11}$[A] at 0~3[V].

• Journal of the Korean Ceramic Society
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• v.30 no.9
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• pp.695-700
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• 1993

In this study, we prepared Pb-Ti stock solution by sol-gel processing and deposited PbTiO3 thin film on a Pt coated SiO2/Si wafer by spin coating using the stock solution. We used lead acetate trihydrate and titanium isopropoxide. The stock solution was partially hydrolized and finally a 0.25M coating solution was prepared. We achieved spin coating at 4000rpm for 30 seconds and heated the thin film at 375$^{\circ}C$ for 5 minutes and at $600^{\circ}C$ for 5 minutes successively, first and second heating state. And the thin film was finally sintered at 90$0^{\circ}C$ for 1 hour in the air. The upper electrode of the thin film was made by gold sputtering and was cricle shape with radius 0.4mm. Measured dielectric constant, dissipation factor and phase transition temperature(Cuire Temp.) were about 275, 0.02 and 521$^{\circ}C$ respectively. To observe ferroelectric characteristics we calculated Pr(remnant polarization) and Ec(coercive field) byhysteresis curve. Ec was 72kV/cm and Pr was 11.46$\mu$C/$\textrm{cm}^2$.

• Proceedings of the KIEE Conference
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• 2002.07c
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• pp.1546-1548
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• 2002

In this paper, the electrical characteristics of pentacene thin film transistors(TFTs) with stacked and surface-treated gate insulators have been investigated. The semiconductor layer of pentacene was thermally evaporated onto the stacked gate insulators. For the gate insulating materials. PVP(PolyvinylPhenol) and polystyrene were spin-coated with two different stacking orders, PVP-polystyrene and polystyrene-PVP. Rapid solvent evaporation during the spin-coating processes of these insulating layers produces non-equilibrium phase morphologies accompanied by surface undulations on gate insulator interfaces. This non-equilibrium phase morphology affects the growth mode of the subsequent pentacene layer. Therefore, in order to smoothen the gate dielectric surfaces, gate dielectric surfaces were rubbed laterally along the direction from the drain to the source TFTs with with stacked and surface-treated gate insulators have provided improved operational characteristics.

• Proceedings of the KIEE Conference
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• 1999.11d
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• pp.918-920
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• 1999

Recently, the ceramics of high permittivity are applied to DRAM and FRAM. In this study, (Ba, Sr)$TiO_3$ (BST) ceramics thin films were prepared by Sol-Gel method. BST solution was made and spin-coated on Pt/$SiO_2$/Si substrate at 4000[rpm] for 10 seconds. Coating process was repeated 3 times and then sintered at $750[^{\circ}C]$ for 30 minutes. Each specimen was analyzed structure and electrical characteristics. Thickness of BST ceramics thin films are about $2000[\AA]$. Dielectric constant and loss of thin films was little decreased at $1[kHz]{\sim}1[MHz]$. Dielectric constant and loss to frequency were 250 and 0.02 in BST3. In accordance with applied voltage, property of leakage current was stability when the was $0{\sim}3$[V]. According to voltage, leakage current was increased exponentially at $4{\sim}7$[V].

• Journal of the Korean Vacuum Society
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• v.13 no.3
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• pp.99-102
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• 2004

In this work the electrical characteristics of organic thin film transistors with the surface-treated organic gate insulator have been studied. For the surface treatment of gate dielectric, Ar plasma was used. Pentacene and PVP were used as active and dielectric layers respectively. Pentacene was thermally evaporated in vacuum at a pressure of about $10^{-6}$ Torr and at a deposition rate of 0.5 $\AA$/sec. PVP was spin coated and cured at $100^{\circ}C$. before pentacene deposition. organic thin film transistors with surface-treated gate insulators have provided improved operation characteristics.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.24 no.11
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• pp.895-899
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• 2011

Multiferroic BFO/PZT(5/95) multilayer films were fabricated by spin-coating method on the Pt/Ti/$SiO_2$/Si substrate alternately using BFO and PZT(9/95) alkoxide solutions. The structural and dielectric properties were investigated with variation of the solvent and the number of coatings. All films showed the typical XRD patterns of the perovskite polycrystalline structure without presence of the second phase such as $Bi_2Fe_4O_3$. BFO/PZT multilayer thin films showed the typical dielectric relaxation properties with increase an applied frequency. The average thickness of 6-coated BFO/PZT multilayer film was about 600 nm. The dielectric properties such as dielectric constant, dielectric loss and remnant polarization were superior to those of single composition BFO film, and those values for BFO/PZT multilayer film were 1199, 0.23% and 12 ${\mu}C/cm^2$.

• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.335-337
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• 1995

In this study, $Pb(Zr_{0.52}Ti_{0.48})O_3$ ceramic thin films were fabricated from an alkoxide-based by Sol-Gel method. $Pb(Zr_{0.52}Ti_{0.48})O_3$ stock solution was made and spin-coated on the $Pt/SiO_2/Si$ substrate at 4000[rpm] for 30[sec]. Coated specimens were dried at 400[$^{\circ}C$] for 10 [min]. The coating process was repeated 4 times and then heat-treated at 500$\sim$800[$^{\circ}C$], 1 hour. The final thickness of the thin films were about 3000[A]. The crystallinity and microstructure of the thin films were investigated for varing the sintering condition. The ferroelectric perovskite' phases precipitated under the sintering of 700[$^{\circ}C$] for 1 hours. In the $Pb(Zr_{0.52}Ti_{0.48})O_3$ thin films sintered at 700[$^{\circ}C$] for 1 hour, dielectric constant and dielectric loss were 2133, 2.2[%] at room temperature, respectively. $Pb(Zr_{0.52}Ti_{0.48})O_3$ thin film capacitors having good dielectric and electrical properties are expected for the application to the dielectric material of DRAM.

• Journal of the Korean Ceramic Society
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• v.45 no.1
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• pp.48-53
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• 2008

In order to reduce signal delay in ULSI, an intermetal material of low dielectric constant is required. Ordered mesoporous silica film is proper to intermetal dielectric due to its low dielectric constant and superior mechanical properties. The ordered mesoporous silica film prepared by TEOS (tetraethoxysilane) / MTES (methyltriethoxysilane) mixed silica precursor and Brij-76 surfactant was surface-modified by HMDS (hexamethyldisilazane) treatment to reduce its dielectric constant. HMDS can substitute $-Si(CH_3)_3$ groups for -OH groups on the surface of silica wall. In order to modify interior silica wall, HMDS was treated by two different processes except the conventional spin coating. One process is that film is dipped and stirred in HMDS/n-hexane solution, and the other process is that film is exposed to evaporated HMDS. Through the investigation with different HMDS treatment, it was concluded that surface modification in evaporated HMDS was more effective to modify interior silica wall of nano-sized pores.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.318.1-318.1
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• 2016

Hafnium Oxide (HfOx) has been attracted as a promising gate dielectric for replacing SiO2 in gate stack applications. In this paper, Metal-Oxide-Semiconductor (MOS) capacitor with solution processed HfO2 high-k material as a dielectric were fabricated. The solvent using $HfOCl2{\cdot}8H2O$ dissolve in 2-Methoxy ethanol was prepared at 0.3M. The HfOx layers were deposited on p-type silicon substrate by spin-coating at $250^{\circ}C$ for 5 minutes on a hot plate and repeated the same cycle for 5 times, followed by annealing process at 350, 450 and $550^{\circ}C$ for 2 hours. When the annealing temperature was increased from 350 to $550^{\circ}C$, capacitance value was increased from 337 to 367 pF. That was resulted from the higher temperature of HfOx which have more crystallization phase, therefore dielectric constant (k) was increased from 11 to 12. It leads to the formation of dense HfOx film and improve the ability of the insulator layer. We confirm that HfOx layer have a good performance for dielectric layer in MOS capacitors.