• Journal of the Microelectronics and Packaging Society
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• v.20 no.2
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• pp.39-46
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• 2013

In this paper, organic solar cells(OSCs) based on bulk-heterojunction structures were fabricated by spin coating method using polymer P3HT and fullerene PCBM as a photoactive layer. The fabricated OSCs had a simple glass/ITO/PEDOT:PSS/P3HT:PCBM/Al structures. The photoactive layer of mixed P3HT:PCBM was formed with 1:1 weight ratio. The hole transport layer(HTL) was used conducting polymer PEDOT:PSS concentration with gold nanoparticles. The annealing temperature and concentration of nanoparticles in HTL were verified to improve the OSC characterization. The percentage of gold nanoparticles in HTL were 0.5 wt% and 1.0 wt%, and the surface morphology, electrical properties and absorption intensities were investigated. The devices were 0.5 wt%, and the highest 3.1% of the powder conversion efficiency(PCE), 10.2 $mA/cm^2$ of the maximum short circuit current density($J_{SC}$), 0.535V of the open circuit voltage($V_{OC}$) and 55.8% of the fill factor(F.F) could be obtained when the nanoparticle concertration was 0.5 wt%. The annealing temperature of HTL was $110^{\circ}C$, $130^{\circ}C$, $150^{\circ}C$ in vacuum oven and measured the absorption intensities, surface morphology, crystallinity and electrical properties were investigated. The best property was obtained in HTL annealed at $130^{\circ}C$ for gold nanoparticles of 0.5 wt%, showing that $J_{SC}$, $V_{OC}$, F.F and PCE were about 12.0 $mA/cm^2$, 0.525V, 64.2% and 4.0%, respectively.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.851-856
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• 2003

We have investigated the material and electrical properties of $Bi_{4-x}La_xTi_3O_{12}$ (BLT) ferroelectric thin film for ferroelectric nonvolatile memory applications of capacitor type and single transistor type. The 120nm thick BLT films were deposited on $Pt/Ti/SiO_2/Si$ and $SiO_2/Nitride/SiO_2$ (ONO) substrates by the sol-gel spin coating method and were annealed at $700^{\circ}C$. It was observed that the crystallographic orientation of BLT thin films were strongly affected by the excess Bi content and the intermediate rapid thermal annealing (RTA) treatment conditions regardeless of two type substrates. However, the surface microstructure and roughness of BLT films showed dependence of two different type substrates with orientation of (111) plane and amorphous phase. As increase excess Bi content, the crystallographic orientation of the BLT films varied drastically in BLT films and exhibited well-crystallized phase. Also, the conversion of crystallographic orientation at intermediate RTA temperature of above $450^{\circ}C$ started to be observed in BLT thin films with above excess 6.5% Bi content and the rms roughness of films is decreased. We found that the electrical properties of BLT films such as the P-V hysteresis loop and leakage current were effectively modulated by the crystallographic orientations change of thin films.

• Journal of the Korean Ceramic Society
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• v.42 no.7 s.278
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• pp.475-482
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• 2005

Zn$_{l-x}$Co$_{x}$O (x = 0.05 - 0.20) films were grown on Coming 7059 glass by sol-gel process. A homogeneous and stable Zn$_{l-x}$Co$_{x}$O sol was prepared by dissolving zinc acetate dihydrate (Zn(CH$_{3}$COO)$_{2}$$\cdot$2H$_{2}$O), cobalt acetate tetrahydrate ((CH$_{3}$)$_{2}$$\cdot$CHOH) and aluminium chloride hexahydrate (AlCl$_{3}$ $\cdot$ 6H$_{2}$O) as solute in solution of isopropanol ((CH$_{3}$)$_{2}$$\cdot$CHOH) and monoethanolamine (MEA:H$_{2}$NCH$_{2}$CH$_{2}$OH). The films grown by spin coating method were postheated in air at 650°C for 1 h and annealed in the condition of vacuum (5 $\times$ 10$^{-6}$ Torr) at 300$^{\circ}C$ for 30 min and investigated the nature of c-axis preferred orientation and physical properties with different Co concentrations. Znl_xCOxO thin films with different Co concentrations were well oriented along the c-axis, but especially a highly c-axis oriented Zn$_{l-x}$Co$_{x}$O thin film was grown at 10 at$\%$ Co concentration. The transmittance spectra showed that Zn$_{l-x}$Co$_{x}$O thin films occur typical d-d transitions and sp-d exchange interaction became activated with increasing Co concentration. The electrical resistivity of the films at 10 at$\%$ Co had the lowest value due to the highest c-axis orientation. X-ray photoelectron spectroscopy and alternating gradient magnetometer analyses indicated that no Co metal cluster was formed, and the ferromagnetic properties appeared, respectively. The characteristics of the electrical resistivity and room temperature ferromagnetism of Zn$_{l-x}$Co$_{x}$O thin films suggested the possibility for the application to dilute magnetic semiconductors.

• Journal of the Korean Ceramic Society
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• v.41 no.2
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• pp.170-175
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• 2004

The ferroelectric (Y $b_{x}$ $Y_{1-x}$)Mn $O_3$ thin films were fabricated by sol-gel method using Y-acetate, Yb-acetate, and Mn-acetate as raw materials. The stable (Y $b_{x}$ $Y_{1-x}$)Mn $O_3$ precursor solution (sol) was prepared through the reflux process with acetylaceton as a catalyst and coated on Si(100) substrate by spin coating. The heat treatment temperature and, Rw ($H_2O$/alkoxide moi ratio) dependence on crystallinity of thin films were studied. The lowest temperature for obtaining YbMn $O_3$phase and the optimum heat-treatment conditions were proved as at 7$50^{\circ}C$ and 80$0^{\circ}C$, respectively. The hexagonal YbMn $O_3$with c-axis preferred orientation could be obtained at Rw=1 condition. The remanent polarization for the thin films of x=0 or 1 was about 200 nC/㎤ while, for the specimens ot 0< x< 1, were 50∼100 nC/$\textrm{cm}^2$.

• Journal of the Korean Magnetics Society
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• v.12 no.2
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• pp.41-45
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• 2002

The low-field tunnel-type magnetoresistance (MR) properties of sol-gel derived $La_{0.7}Pb_{0.3}MnO_3(LPMO)$ thin film deposited on different substrate have been investigated. Polycrystalline thin films were fabricated by spin-coating on $SiO_2/Si(100)$ substrate and that with yttria-stabilized zirconia (YSZ) buffer layer, while c-axis-oriented thim film was grown on $LaAlO_3(001)$ (LAO) single crystal substrate. The full width half maximum (FWHM) of the rocking curve scan of LPMO/LAO film is $0.32^{\circ}$. Tunnel-type MR ratio is 0.52 % in $LPMO/SiO_2/Si$(100) film and that of $LPMO/YSZ/SiO_2/Si$(100) film is as high as 0.68 %, whereas that of LPMO/LAO(001) film is less than 0.4 % under the applied field of 500 Oe at 300 K. Well-pronounced MR hysteresis was registered with an MR peak in the vicinity of the coercive field. The low-field tunnel-type MR characteristics of thin films deposited on different substrates originates from the behavior of grain boundary properties.

• Korean Journal of Optics and Photonics
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• v.21 no.1
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• pp.33-37
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• 2010

We performed time-domain terahertz (THz) spectroscopy to determine optical constants of highly conductive carbon nanotube (CNT) films. The CNT films have been fabricated on a flexible plastic substrate by using spin-coating or vacuum filtration. We found that the transmission of THz waves can be controlled by manipulating the thickness of the films and by post-treatments. From amplitude and phase information of the transmitted THz waves, we obtain optical constants such as refractive indices and dielectric constants of the CNT films. The frequency dependent dielectric constants show good metallic behaviors, relevant to the Drude free electron models with high plasma frequencies. It is also found that the dielectric constants are higher for the acid-treated films. Finally, the frequency dependent dielectric constants which are free from substrate effects have been demonstrated by using CNT films deposited on cellulose membranes.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.344-344
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• 2014

Transparent amorphous oxide semiconductors such as a In-Ga-Zn-O (a-IGZO) have advantages for large area electronic devices; e.g., uniform deposition at a large area, optical transparency, a smooth surface, and large electron mobility >10 cm2/Vs, which is more than an order of magnitude larger than that of hydrogen amorphous silicon (a-Si;H).1) Thin film transistors (TFTs) that employ amorphous oxide semiconductors such as ZnO, In-Ga-Zn-O, or Hf-In-Zn-O (HIZO) are currently subject of intensive study owing to their high potential for application in flat panel displays. The device fabrication process involves a series of thin film deposition and photolithographic patterning steps. In order to minimize contamination, the substrates usually undergo a cleaning procedure using deionized water, before and after the growth of thin films by sputtering methods. The devices structure were fabricated top-contact gate TFTs using the a-IGZO films on the plastic substrates. The channel width and length were 80 and 20 um, respectively. The source and drain electrode regions were defined by photolithography and wet etching process. The electrodes consisting of Ti(15 nm)/Al(120 nm)/Ti(15nm) trilayers were deposited by direct current sputtering. The 30 nm thickness active IGZO layer deposited by rf magnetron sputtering at room temperature. The deposition condition is as follows: a rf power 200 W, a pressure of 5 mtorr, 10% of oxygen [O2/(O2+Ar)=0.1], and room temperature. A 9-nm-thick Al2O3 layer was formed as a first, third gate insulator by ALD deposition. A 290-nm-thick SS6908 organic dielectrics formed as second gate insulator by spin-coating. The schematic structure of the IGZO TFT is top gate contact geometry device structure for typical TFTs fabricated in this study. Drain current (IDS) versus drain-source voltage (VDS) output characteristics curve of a IGZO TFTs fabricated using the 3-layer gate insulator on a plastic substrate and log(IDS)-gate voltage (VG) characteristics for typical IGZO TFTs. The TFTs device has a channel width (W) of $80{\mu}m$ and a channel length (L) of $20{\mu}m$. The IDS-VDS curves showed well-defined transistor characteristics with saturation effects at VG>-10 V and VDS>-20 V for the inkjet printing IGZO device. The carrier charge mobility was determined to be 15.18 cm^2 V-1s-1 with FET threshold voltage of -3 V and on/off current ratio 10^9.

• Korean Journal of Materials Research
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• v.9 no.8
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• pp.804-809
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• 1999

Silica films were prepared on Si single crystal substrates by a sol-gel process without DMF using TEOS as a starting material. Films were fabricated by spin coating technique. For films having a composition of TEOS : HCI(1:0.05mol), gelation time, the thickness of films, the formation of cracks and the microstructure of the films were investigated as a function of the molar ratio of $CH_3OH and H_2O$. With 8mol $CH_3OH$, the longest gelation time was measured to be 640hr. The thickness of the coated films was decreased with increasing content of $CH_3OH$. The films were sintered at $500^{\circ}C$ for 1hr with a heating rate of $0.6^{\circ}C$/min. The coated films showed worm-like grains and partially cracked microstructures at an amount of $CH_3OH$ 2mol and 4mol. The addition of more than 8 mole of $CH_2OH$ resulted in crack-free silica films. This suggests that crack-free films can be fabricated by controlling the surface tension energy of the sol solutions without DMF.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.4
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• pp.20-25
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• 2020

As nanoscience and nanotechnology advance, techniques for selective pattern growth have attracted significant attention. Silica nanoparticles (NPs) are used as a promising nanomaterials for bio-labeling, bio-imaging, and bio-sensing. In this study, silica NPs were synthesized by a sol-gel process using a modified Stöber method. In addition, the selective pattern growth of silica NPs was achieved by the surface functionalization of the substrate using a micro-contact printing technique of a hydrophobic treatment. The particle size of the as-synthesized silica NPs and morphology of selective pattern growth of silica NPs were characterized by FE-SEM. The contact angle by surface functionalization of the substrate was investigated using a contact angle analyzer. As a result, silica NPs were not observed on the hydrophobic surface of the OTS solution treatment, which was coated by spin coating. In contrast, the silica NPs were well coated on the hydrophilic surface after the KOH solution treatment. FE-SEM confirmed the selective pattern growth of silica NPs on a hydrophilic surface, which was functionalized using the micro-contact printing technique. If the characteristics of the selective pattern growth of silica NPs can be applied to dye-doped silica NPs, they will find applications in the bio imaging, and bio sensing fields.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.