• Proceedings of the KIEE Conference
• /
• 1992.07b
• /
• pp.645-648
• /
• 1992

In a capacitor-discharge impulse magnetizer, one of the magnetic application system, a magnet is magnetized by the discharging current of capacitors. The conventional design of the magnetizer has been based on many year's experience. The behaviour of flux in the magnetizer should be calculated in order to produce the desired magnets. The analysis of the flux distribution is quite difficult. This is because both the magnetizing current and the applied voltage to the magnetizer are unknown. This paper describes the development of computer model for a capacitor-discharge impulse magnetizer using SPICE. Also, the detailed distribution of the flux density in a magnet magnetized by the impulse magnetizer be analyed.

• Journal of Astronomy and Space Sciences
• /
• v.17 no.1
• /
• pp.99-106
• /
• 2000

When a deployed probe is biased by a high positive potential during a space experiment, the payload is induced to a negative voltage in order to balance the total current in the whole system. The return currents are due to the responding ions and secondary electrons on the payload surface. In order to understand the current collection mechanism, the process was simulated with a combination of resistor, inductor, and capacitor in SPICE program which was equivalent to the background plasma sheath. The simulation results were compared with experimental results from SPEAR-3 (Space Power Experiment Aboard Rocket-3). The return current curve in the simulation was compatible to the experimental result, and the simulation helped to predict the transient plasma response to a high voltage during the plasma sheath formation.

• Proceedings of the KIEE Conference
• /
• 1987.07b
• /
• pp.1560-1563
• /
• 1987

This paper is concerned with time delay modeling of ED MOS gates which takes into account the slope of input waveform as well as the load condition. Defining the delay time as the time required to charge/discharge the load to the physical reference level, the rise/fall delay times arc derived in an explicit formula in terms of the sum of optimally weighted current unbalances at two end points of voltage transition. The proposed model is computationally effective and the error is typically within 10% of the SPICE results.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.10
• /
• pp.94-100
• /
• 1994

By using the RAPHAEL 3D inductance calculation program RI3, the PGA package inductance values of INTEL i486 microprocessor have been extracted. The lead frame layouts are drawn using the mentor Boardstation and the output files are converted into the RI3 program input format of RAPHAEL. The power and ground planes of the PGA package are modeled y grid-line structures of single bars. The capacitance valuse of signal lines have been clalculated by using the RAPHAEL 2D/3D capacitance extraction program. The extraced L, C, R values have been converted into the SPICE netlist formats with lumped circuit model for future use in the signal ingegrity analysis.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2003.07a
• /
• pp.642-645
• /
• 2003

We proposed new current source and mirror circuits insensitive to $V_{th}$ variation of poly-Si TFTs. The proposed circuits have been verified by SPICE simulation using poly-Si TFT model. The error currents of the proposed current source and current mirror circuits caused by $V_{th}$ variation reduced less than 6.6% and 4.5% of that of conventional ones, respectively.

• Proceedings of the IEEK Conference
• /
• 2000.11b
• /
• pp.9-12
• /
• 2000

InP/lnGaAs heterojunciton phototransistors (HPTs) with transparent emitter contacts were fabricated and characterized. Indium Tin Oxide was RF sputtered for the emitter contacts. By comparison with InP/InGaAs HBTs, the dc characteristics of InP/lnGaAs HPTs demonstrated offset voltage due to ITO emitter contacts and similar common emitter current gain. The model parameters were extracted and a simple SPICE simulations were performed.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.2
• /
• pp.184-195
• /
• 1996

Beause BiCMOS logic circuits consist of CMOS part which constructs logic function and bipolar part which drives output load, the effect of short faults on BiCMOS logic circuits represented different types from that on CMOS. This paper proposes new test method which detects short faults on BiCMOS logic circuits using current path graph. Proposed method transforms BiCMOS circuits into raph constructed by nodes and edges using extended switch-level model and separates the transformed graph into pull-up part and pull-down part. Also, proposed method eliminates edge or add new edge, according ot short faults on terminals of transistor, and can detect short faults using current path graph that generated from on- or off-relations of transistor by input patterns. Properness of proposed method is verified by comparing it with results of spice simulation.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.33A no.5
• /
• pp.180-187
• /
• 1996

This paper describes a post-layout simulation method using VHDL and C for verifying the architecture of antifuse-based FPGAs and the dedicated CAD system. An antifuse-based FPGA consists of programming circuitry including decoding logic, logic modules, segmented tracks, antifuses and I/O pads. The VHDL model which includes all these elements is used for logic verification and programming verification of the implemented circuit by reconstructing the logic circuit from the bit-stream generated from layout tool. The implemented circuit comprises of logic modules and routing networks. Since the routing delay of the complex networks is comparable to the delay of the logic module in the FPGA, the accurate post-layout simulation is essential to the FPGA system. In this paper, the C program calculates the delay of the routing netowrks using SPICE, elmore or horowitz delay models and the results feedback to the VHDL simulation. Critical path anc be found from this post-layout simulation results.

• Journal of Korean Society for Quality Management
• /
• v.34 no.3
• /
• pp.1-18
• /
• 2006

CMMI(Capability Maturity Model Integration) has been recognized as a critical method to validate the competitiveness of software development organization since its introduction. CMMI imposes additional requirements on the software development organization which has been established and certified to the ISO 9001 quality management system. This paper reviews the similarities and differences between CMMI and ISO 9001. This paper also examines what ate required to deploy the CMMI on the aircraft software development organization which has been certified to ISO 9001. The results of this study will help software development organization to provide the direction for implementing CMMI. Some suggestions are presented to identify and strengthen the weak portion of the software process quality management system.

• Journal of the Korean Institute of Telematics and Electronics A
• /
• v.31A no.4
• /
• pp.116-126
• /
• 1994

In this paper, the switch-level fault simulator for CMOS circuits with a gate-to-drain/source short fault is implemented. A fault model used in this paper is based on the graphical analysis of the electrical characteristics of the faulty MOS devices and the conversion of the faulty CMOS circuit to the equivalent faulty CMOS inverter in order to find its effect on the successive stage. This technique is very simple and has the increased accuracy of the simulation. The simulation result of the faulty circuit using the implemented fault simulator is compared with the result of the SPICE simulation.