• JSTS:Journal of Semiconductor Technology and Science
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• 제15권5호
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• pp.485-489
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• 2015

An accurate large-signal BSIM4 macro model including new empirical bias-dependent equations of the drain-source capacitance and channel resistance constructed from bias-dependent data extracted from S-parameters of RF MOSFETs is developed to reduce $S_{22}$-parameter error of a conventional BSIM4 model. Its accuracy is validated by finding the much better agreement up to 40 GHz between the measured and modeled $S_{22}$-parameter than the conventional one in the wide bias range.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권3호
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• pp.139-144
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• 2003

We report the results of extensive mixed mode simulations and theoretical analysis to quantify the contribution of the edge direct tunneling (EDT) current on the total gate leakage current of 80nm NMOSFET with SiO2 gate dielectric. It is shown that EDT has a profound impact on basic analog circuit building blocks such as sample-hold (S/H) circuit and the current mirror circuit. A transistor design methodology with zero gate-source/drain overlap is proposed to mitigate the EDT effect. This results in lower voltage droop in S/H application and better current matching in current mirror application. It is demonstrated that decreasing the overlap length also improves the basic analog circuit performance metrics of the transistor. The transistor with zero gate-source/drain overlap, results in better transconductance, input resistance, output resistance, intrinsic gain and unity gain transition frequency.

• Applied Science and Convergence Technology
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• 제26권5호
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• pp.129-132
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• 2017

We report a chemical vapor deposition approach and optimized growth condition to the synthesis of single layer molybdenum disulfide ($MoS_2$). Obtaining large grain size with continuous $MoS_2$ atomically thin films is highly responsible to the growth distance between molybdenum trioxide source and receiving silicon substrate. Experimental results indicate that triangular shape $MoS_2$ grain size could be enlarged up to > 80um with the precisely controlled the source-to-substrate distance under 7.5 mm. Furthermore, we demonstrate fabrication of a memory device by employing poly(methyl methacrylate) (PMMA) as insulating layer. The fabricated devices have a PMMA-$MoS_2$/metal configuration and exhibit a bistable resistance switching behavior with high/low-current ratio around $10^3$.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2011년도 제41회 하계 정기 학술대회 초록집
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• pp.177-179
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• 2011

The purpose of this study is to enhance an adhesion between substrate and Diamond-like Carbon (DLC) film. DLC has many outstanding properties such as low friction, high wear resistance and corrosion resistance. However, it is difficult to achieve enough adhesion because of weak bonding between DLC film and the substrate. For improvement adhesion, a layer between DLC film and the substrate was prepared by dual post plasma. DLC film was deposited on nitrided layer by linear ion source. The composed compound layer between substrate and DLC film was investigated by Glow Discharge Spectrometer (GDS) and Scanning Electron Microscope (SEM). The synthesized bonding structure of DLC film was analyzed using a micro raman spectrometer. Mechanical properties were measured by nano-indentation. In order to clarify the mechanism for improvement in adhesive strength, it was observed by scratch test.

• Journal of Information Display
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• 제5권1호
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• pp.1-6
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• 2004

Ion shower doping with a main ion source of $P_2H_x$ using a source gas mixture of $PH_3/H_2$ was conducted on excimer-laser- annealed (ELA) poly-Si. The crystallinity of the as-implanted samples was measured using a UV-transmittance. The measured value of as-implanted damage was found to correlate well with the one calculated through/obtained from TRIM-code simulation. The sheet resistance was found to decrease as the acceleration voltage increased from 1 kV to 15 kV at a doping time of 1 min. However, it increases as the acceleration voltage increases under severe doping conditions. Uncured damage after furnace annealing is responsible for the rise in sheet resistance.

• 대한전기학회논문지
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• 제43권6호
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• pp.951-957
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• 1994

We present a new model for the series resistance of inverted-staggered amorphous silicon (a-Si) thin film transistors (TFT's) by employing the current spreading under the source and the drain contacts as well as the space charge limited current model. The calculated results based on our model have been in good agreements with the measured data over a wide range of applied voltage, gate-to-source and gate-to-drain overlap length, channel length, and operating temperature. Our model shows that the contribution of the series resistances to the current-voltage (I-V) characteristics of the a-Si TFT in the linear regime is more significant at low drain and high gate voltages, for short channel and small overlap length, and at low operating temperature, which have been verified successfully by the experimental measurements.

• Journal of Hydrospace Technology
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• 제2권2호
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• pp.36-43
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• 1996

In this work, a panel method is described, which cart solve the flow field round a surface-piercing body that experiences lift and wave resistance. As the body boundary condition, a Dirichlet type is employed, and as the free surface boundary condition the Poisson type is implemented, while in its discretization Dawson's 4-point upwind difference scheme is utilized, and as the Kutta condition a Morino-Kuo type is chosen. As to the type of singularity, source panels are distributed on the free surface, and source and dipole panels on the body surface, and dipole panels on the wake surface. For a sample run, a catamaran of the parabolic Wigley hull is chosen, for which experimental data are available, and the predictions by the numerical means and by the experiment are compared for a wide range of parameters.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2007년도 제38회 하계학술대회
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• pp.73-74
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• 2007

For a safe operation of HVDC systems, the fault location and clearance of faults in the HVDC lines are important. Past methods for fault location on HVDC cable depend on existence of assistance cables and fault resistance, broken cable and environment of fault location. For complement these problems, in this paper, fault location method using traveling wave and cross correlation function is proposed for HVDC cables. Voltage controlled source and current controlled source HVDC were modeled by EMTDC/PSCAD. The proposed algorithm were verified varying with fault distance, fault resistance.

• International Journal of Naval Architecture and Ocean Engineering
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• 제7권3호
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• pp.478-489
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• 2015

In the present study, a hydrodynamic hull-form optimization algorithm for a container ship was presented in terms of the minimum wave-making resistance. Bell-shaped modification functions were developed to modify the original hull-form and a sequential quadratic programming algorithm was used as an optimizer. The wave-making resistance as an objective function was obtained by the Rankine source panel method in which non-linear free surface conditions and the trim and sinkage of the ship were fully taken into account. Numerical computation was performed to investigate the validity and effectiveness of the proposed hull-form modification algorithm for the container carrier. The computational results were validated by comparing them with the experimental data.

• Journal of Electrical Engineering and Technology
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• 제13권6호
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• pp.2212-2219
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• 2018

This paper describes extended fault location algorithm using estimated remote source impedance. The method uses data only at the local end and the sequence current distribution factors for more accurate estimation. The proposed algorithm can respond to variation of the local and remote source impedance. Therefore, this method is especially useful for transmission lines interconnected to a wind farm that the source impedance varies continuously. The proposed algorithm is very insensitive to the variation in fault distance and fault resistance. The simulation results have shown the accuracy and effectiveness of the proposed algorithm.