• Journal of KIISE:Computing Practices and Letters
• /
• v.12 no.1
• /
• pp.43-55
• /
• 2006

In this paper, we present a framework which is used to develop, modify, maintain and extend a control and monitoring software easily for any kind of automatic instruments. The proposed framework is composed of three XML documents (IID, MAP, CMIML) and two tools (Virtual Instrument Wizard, Generator). Interface information of behaviors and states of instrument is written on IID. Mapping information between the interface information in IID and API of a real instrument driver is written on MAP Final information of the control and monitoring software is written on CMIML, IID, MAP and CMIML are written by XML format to provide a common usage and platform independence of the proposed framework. Vl Wizard generates CMIML intermediate platform independent document using IID and existing CMIML, and Generator generates the source code of a control and monitoring software platform dependent code automatically using CMIML and MAP. The suggested framework provides an easy development and maintenance because it automatically generates a control and monitoring software in GUI environment and it also provides common usage and platform independence in virtue of using description document of XML format. Also, reusability can be increased by reusing platform independent software description document and not reusing platform dependent software code.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.43 no.3 s.345
• /
• pp.21-32
• /
• 2006

A new SRAM circuit with row-by-row activation and low-swing write schemes is proposed to reduce switching power of active cells as well as leakage one of sleep cells in this paper. By driving source line of sleep cells by $V_{SSH}$ which is higher than $V_{SS}$, the leakage current can be reduced to 1/100 due to the cooperation of the reverse body-bias. Drain Induced Barrier Lowering (DIBL), and negative $V_{GS}$ effects. Moreover, the bit line leakage which may introduce a fault during the read operation can be eliminated in this new SRAM. Swing voltage on highly capacitive bit lines is reduced to $V_{DD}-to-V_{SSH}$ from the conventional $V_{DD}-to-V_{SS}$ during the write operation, greatly saving the bit line switching power. Combining the row-by-row activation scheme with the low-swing write does not require the additional area penalty. By the SPICE simulation with the Berkeley Predictive Technology Modes, 93% of leakage power and 43% of switching one are estimated to be saved in future leakage-dominant 70-un process. A test chip has been fabricated using $0.35-{\mu}m$ CMOS process to verify the effectiveness and feasibility of the new SRAM, where the switching power is measured to be 30% less than the conventional SRAM when the I/O bit width is only 8. The stored data is confirmed to be retained without loss until the retention voltage is reduced to 1.1V which is mainly due to the metal shield. The switching power will be expected to be more significant with increasing the I/O bit width.