• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.4
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• pp.117-123
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• 2013

In the recent cloud storage environment, the amount of SSD (Solid-State Drive) replacing with the traditional hard disk drive is increasing. Management of SSD for its space efficiency has become important since SSD provides fast IO performance due to no mechanical movement whereas it has wearable characteristics and does not provide in place update. In order to manage space efficiency of SSD, data de-duplication technique is frequently used. However, this technique occurs much overhead because it consists of data chunking, hasing and hash matching operations. In this paper, we propose new data de-duplication method using PRAM cache. The proposed method uses hierarchical hash tables and LRU(Least Recently Used) for data replacement in PRAM. First hash table in DRAM is used to store hash values of data cached in the PRAM and second hash table in PRAM is used to store hash values of data in SSD storage. The method also enhance data reliability against power failure by maintaining backup of first hash table into PRAM. Experimental results show that average writing frequency and operation time of the proposed method are 44.2% and 38.8% less than those of existing data de-depulication method, respectively, when three workloads are used.

• Journal of Internet Computing and Services
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• v.16 no.5
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• pp.19-27
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• 2015

Due to the advantages of fast read/write operation and low power consumption, SSD(Solid State Drive) is now widely adopted as storage device of smart phone, laptop computer, server, etc. However, the shortcomings of SSD such as limited number of write operations and asymmetric read/write operation lead to the problem of shortened life span of SSD. Therefore, the block replacement policy of SSD used as cache for HDD is very important. The existing solutions for improving the lifespan of SSD including the LARC scheme typically employ the LRU algorithm to manage the SSD blocks, which may increase the miss rate in SSD due to the replacement of frequently used block instead of rarely used block. In this paper we propose a novel block replacement scheme which considers the block reuse interval to effectively handle various data read/write patterns. The proposed scheme replaces the block in SSD based on the recency decided by reuse interval and age along with hit ratio. Computer simulation using workload trace files reveals that the proposed scheme consistently improves the performance and lifespan of SSD by increasing the hit ratio and decreasing the number of write operations compared to the existing schemes including LARC.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.1115-1116
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• 2008

Through comparison and evaluation of various HDD systems for PC such as magnetic HDD, Intel turbo memory and Solid State Drive (SSD), an optimized HDD system to improve booting speed proposed. For the study, conventional magnetic HDD, magnetic HDD with Intel turbo memory, SSD and SSD with Intel turbo memory are used. The evaluation is performed based on a full notebook machine with Intel SantaRosa platform and MicroSoft Windows Vista.

• Proceedings of the KAIS Fall Conference
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• 2010.11a
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• pp.168-171
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• 2010

본 논문에서는 GaN HEMT 소자를 이용한 고출력 고효율 특성을 가지는 광대역 SSPA의 개발을 다루고 있다. 개발한 SSPA는 8W 급과 15W 급의 GaN HEMT 소자를 사용하여 Pre-Drive 증폭단을 구성하였으며, Drive 증폭단은 50W/150W급 GaN HEMT 소자를 직/병렬구조로 사용하였다. Main 증폭단은 4-way 분배기와 결합기를 이용한 Balanced Structure를 적용하여 높은 출력을 구현하였으며, 안정적인 동작을 위하여 음(-)전원 제어 회로와 출력신호 검출 회로를 포함하고 있다. 제작된 SSPA의 사용가능 대역은 2.9GHz~3.3GHz로 단일전원을 사용하고 있으며 100us 펄스 폭, 10% Duty Cycle 조건에서 60dB의 전압이득, 1kW 출력과 약 28% 효율 특성을 가지는 것으로 측정되었다. 본 논문에서 개발한 SSPA는 S-대역을 사용하는 레이더시스템의 송신단에 적용될 수 있다.

• Proceedings of the Korean Society of Computer Information Conference
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• 2014.07a
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• pp.353-354
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• 2014

오늘날 데이터베이스 시스템 의 스토리지에 많은 정보를 저장하게 되는데 이때 주로 HDD가 사용되고 있으며, 지금까지 대용량 저장 장치로 발전을 해왔다. HDD는 단위 비트 당 가격이 저렴한 이점이 있으나 HDD를 이용한 저장장치는 낮은 수행 속도 때문에 빠르게 정보를 제공받기를 원하는 사용자의 요구를 충족시키지 못하고 있다. 이를 해결하기 위해 빠른 I/O속도를 갖는 SSD를 이용한 저장 장치가 연구가 많이 되고 있으나 비트 당 가격이 비싼 SSD의 단점으로 인해 HDD를 전부 SSD로 대체하기에는 어려움이 있다. 본 논문에서는 HDD를 SSD로 완전히 대체하는 시스템이 아니라 SSD를 캐시로 사용한 SSD의 기반으로 혼합 스토리지 구조를 이용하여 검색 성능을 최적화시키기 위한 방법을 제안한다.

• Annual Conference of KIPS
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• 2011.11a
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• pp.28-29
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• 2011

SSD(Solid State Drive)는 다중-채널/ 다중-웨이 방식의 NAND 플래시 메모리를 이용하는 저장장치로서 기존 HDD(Hard Disk Drive)를 대체할 차세대 보조기억장치로 주목받고 있다. 하지만 SSD 와 같은 동작을 하는 커널레벨의 시뮬레이터가 존재하지 않아, 사용자 영역에서부터 실제 NAND 플래시 칩까지의 동작 원리를 파악하기 어렵다. 이러한 문제를 해결하기 위해 본 논문에서는 SSD 시뮬레이터의 설계 및 구현내용을 기술한다. 구현한 SSD 시뮬레이터는 다중-채널/ 다중-웨이 방식의 SSD 전체적인 동작 원리를 리눅스 커널 수준에서 파악할 수 있다. 또한 FTL 개발을 위한 환경을 제공할 뿐만 아니라, 사용자가 다양한 SSD 구조를 설계하여 성능을 예측할 수 있도록 한다.

• Annual Conference of KIPS
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• 2022.11a
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• pp.721-723
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• 2022

최근 낸드 플래시 메모리 기반의 Solid State Drive(SSD)가 기존 Hard Disk Drive(HDD)를 대신하여 개인용과 산업용으로도 널리 쓰이고 있다. 핫 데이터 구분 기법은 이러한 SSD 의 성능과 수명에 중요한 역할을 하는 Garbage Collection(GC)과 Wear Leveling(WL) 기술의 기반이 된다. 본 논문에서는 핫 데이터를 예측하기 위한 나이브 베이즈 분류 기반의 새로운 핫 데이터 구분 기법을 제안한다. 제안 기법은 워크로드 액세스 패턴의 학습 단계인 초기 단계와 실제 운영 단계를 통해 다시 액세스 될 확률이 높은 데이터를 그렇지 않은 데이터와 효과적으로 구분한다. 다양한 실제 trace 기반 실험을 통해 본 제안 기법이 기존 대표적인 기법보다 평균 19.3% 높은 성능을 확인했다.

• ETRI Journal
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• v.36 no.5
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• pp.876-879
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• 2014

In current NAND flash design, one of the most challenging issues is reducing peak current consumption (peak ICC), as it leads to peak power drop, which can cause malfunctions in NAND flash memory. This paper presents an efficient approach for reducing the peak ICC of the cache program in NAND flash memory - namely, a program Cache Busy Time (tPCBSY) control method. The proposed tPCBSY control method is based on the interesting observation that the array program current (ICC2) is mainly decided by the bit-line bias condition. In the proposed approach, when peak ICC2 becomes larger than a threshold value, which is determined by a cache loop number, cache data cannot be loaded to the cache buffer (CB). On the other hand, when peak ICC2 is smaller than the threshold level, cache data can be loaded to the CB. As a result, the peak ICC of the cache program is reduced by 32% at the least significant bit page and by 15% at the most significant bit page. In addition, the program throughput reaches 20 MB/s in multiplane cache program operation, without restrictions caused by a drop in peak power due to cache program operations in a solid-state drive.

• KIISE Transactions on Computing Practices
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• v.24 no.3
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• pp.129-137
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• 2018

NVMe(Non-Volatile Memory Express) SSD(Solid State Drive) is a high-performance storage that makes use of flash memory as a storage cell, PCIe as an interface and NVMe as a protocol on the interface. It supports multiple I/O queues which makes it feasible to process parallel-I/Os on multi-core environments and to provide higher bandwidth than SATA SSDs. Hence, NVMe SSD is considered as a next generation-storage for data-center and cloud computing system. However, in the virtualization system, the performance of NVMe SSD is not fully utilized due to the bottleneck of the software I/O stack. Especially, when it uses I/O stack of the hypervisor or the host operating system like Xen and KVM, I/O performance degrades seriously due to doubled-I/O stack between host and virtual machine. In this paper, we propose a new I/O engine, called Direct-AIO (Direct-Asynchronous I/O) engine, that can access NVMe SSD directly for I/O performance improvements on QEMU emulator. We develop our proposed I/O engine and analyze I/O performance differences between the existed I/O engine and Direct-AIO engine.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.45-52
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• 2011

Flash memory is becoming widely prevalent in various area due to high performance, non-volatile features, low power, and robust durability. As price-per-bit is decreased, NAND flash based SSDs (Solid State Disk) have been attracting attention as the next generation storage device, which can replace HDDs (Hard Disk Drive) which have mechanical properties. Especially for the single package SSD, if channel number or FIFO buffer size per channel increases to improve performance, the size of a controller and I/O pin count will increase linearly with channel numbers and form factor will be affected. We propose a novel technique which can minimize form factor by optimizing the number of NAND flash channels and the size of interface FIFO buffer in the SSD. For SSD with 10 channel and double buffer, the experimental results show that buffer block size can be reduced about 73% without performance degradation and total size of a controller can be reduced about 40% because control block per channel and I/O pin count decrease according to decrease channel number.