• Proceedings of the IEEK Conference
• /
• 2002.06b
• /
• pp.165-168
• /
• 2002

As the demand for higher data-rate chip-to-chip communication such as memory-to-controller, processor-to-processor increases, low cost high-speed serial links\ulcorner become more attractive. This paper describes a 0.25-fm CMOS 1.6Gbps/pin 4-level transceiver using Stub Series Terminated Logic for high Bandwidth. For multi-gigabit/second application, the data rate is limited by Inter-Symbol Interference (ISI) caused by channel low pass effects, process-limited on-chip clock frequency, and serial link distance. The proposed transceiver uses multi-level signaling (4-level Pulse Amplitude Modulation) using push-pull type, double data rate and flash sampling. To reduce Process-Voltage-Temperature Variation and ISI including data dependency skew, the proposed high-speed calibration circuits with voltage swing controller, data linearity controller and slew rate controller maintains desirable output waveform and makes less sensitive output. In order to detect successfully the transmitted 1.6Gbps/pin 4-level data, the receiver is designed as simultaneous type with a kick - back noise-isolated reference voltage line structure and a 3-stage Gate-Isolated sense amplifier. The transceiver, which was fabricated using a 0.25 fm CMOS process, performs data rate of 1.6 ~ 2.0 Gbps/pin with a 400MHB internal clock, Stub Series Terminated Logic ever in 2.25 ~ 2.75V supply voltage. and occupied 500 * 6001m of area.

• Journal of KIISE:Information Networking
• /
• v.32 no.6
• /
• pp.668-675
• /
• 2005

With the proliferation of wireless network and the advances of the embedded systems, the traditional distributed systems begin to include the wireless embedded systems. Clock synchronization in the distributed systems is one of the major issues that should be considered for diverse Purposes including synchronization, ordering, and consistency. Many clock synchronization algorithms have been proposed over the years. Since clock synchronization in wireless embedded systems should consider the low bandwidth of a network and the poor resources of a system, most traditional algorithms cannot be applied directly. We propose a clock synchronization algorithm in wireless embedded systems, extending IEEE 802.11 standard. The proposed algorithm can not only achieve high precision by loosening constraints and utilizing the characteristics of wireless broadcast but also provide continuous time synchronization by tolerating the message losses. In master/slave structure the master broadcasts the time information and the stave computes the clock skew and the drift to estimate the synchronized time of the master. The experiment results show that the achieved standard deviation by the Proposed scheme is within the bound of about 200 microseconds.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.26 no.12C
• /
• pp.255-260
• /
• 2001

This paper describes the design of the Register Controlled DLL(Delay-Locked Loop) that achieves fast locking and low Power consumption using a new locking algorithm. A fashion for a fast locking speed is that controls the two controller in sequence. The up/down signal due to clock skew between a internal and a external clock in phase detector, first adjusts a large phase difference in coarse controller and then adjusts a small phase difference in fine controller. A way for a low power consumption is that only operates one controller at once. Moreover the proposed DLL shows better jitter performance Because using the lock indicator circuit. The proposed DLL circuit is operated from 50MHz to 200MHz by SPICE simulation. The estimated power dissipation is 15mA at 200MHz in 3.3V operation. The locking time is within 7 cycle at all of operating frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.6
• /
• pp.18-24
• /
• 2012

This paper reports the test results of a 50MHz/s 10 bits DAC developed with $0.18{\mu}m$ CMOS process for the wireless sensor network application. The 10bits DAC, not likely a typical segmented type, has been designed as a current driving type with double step thermometer decoding architecture in which 10bits are divided into 6bits of MSB and 4bits of LSB. MSB 6bits are converted into 3 bits row thermal codes and 3 bits column thermal codes to control high current cells, and LSB 4 bits are also converted into thermal codes to control the lower current cells. The high and the lower current cells use the same cell size while a bias circuit has been designed to make the amount of lower unit current become 1/16 of high unit current. All thermal codes are synchronized with output latches to prevent glitches on the output signals. The test results show that the DAC consumes 4.3mA DC current with 3.3V DC supply for 2.2Vpp output at 50MHz clock. The linearity characteristics of DAC are the maximum SFDR of 62.02dB, maximum DNL of 0.37 LSB, and maximum INL of 0.67 LSB.

• Journal of Radiation Protection and Research
• /
• v.40 no.4
• /
• pp.216-222
• /
• 2015

Facilities processing raw materials containing naturally occurring radioactive materials (NORM) may give rise to enhanced radiation dose to workers due to chronic inhalation of airborne particulates. Internal radiation dose due to particulate inhalation varies depending on particulate properties, including size, shape, density, and absorption type. The objective of the present study was to assess inhalation dose sensitivity to physicochemical properties of airborne particulates. Committed effective doses to workers resulting from inhalation of airborne particulates were calculated based on International Commission on Radiological Protection 66 human respiratory tract model. Inhalation dose generally increased with decreasing particulate size. Committed effective doses due to inhalation of $0.01{\mu}m$ sized particulates were higher than doses due to $100{\mu}m$ sized particulates by factors of about 100 and 50 for $^{238}U$ and $^{230}Th$, respectively. Inhalation dose increased with decreasing shape factor. Shape factors of 1 and 2 resulted in dose difference by about 18 %. Inhalation dose increased with particulate mass density. Particulate mass densities of $11g{\cdot}cm^{-3}$ and $0.7g{\cdot}cm^{-3}$ resulted in dose difference by about 60 %. For $^{238}U$, inhalation doses were higher for absorption type of S, M, and F in that sequence. Committed effective dose for absorption type S of $^{238}U$ was about 9 times higher than dose for absorption F. For $^{230}Th$, inhalation doses were higher for absorption type of F, M, and S in that sequence. Committed effective dose for absorption type F of $^{230}Th$ was about 16 times higher than dose for absorption S. Consequently, use of default values for particulate properties without consideration of site specific physiochemical properties may potentially skew radiation dose estimates to unrealistic values up to 1-2 orders of magnitude. For this reason, it is highly recommended to consider site specific working materials and conditions and use the site specific particulate properties to accurately access radiation dose to workers at NORM processing facilities.