• Fashion & Textile Research Journal
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• v.6 no.3
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• pp.347-356
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• 2004

The purpose of this study is to analyze the sizing system and size designation of ready-made jackets for women. We survey the sizing system and size labeling that have been used and presently practiced by the domestic garment industry of ready-made woman's jacket. In addition, 264 tailored jackets are measured for the sake of this study. The jackets are classified into 3 groups(young, missy, and madame) according to the target age of the brand. The result shows that size labeling involves body measurements(85-94-160), size code(55, 66) or simplified letter(S, M, L). However, the correspondence of size information and ease tolerances of jackets is not consistent and each company has its own sizing system. There are significant differences among young, missy, and madame group on the bust girth of apparel in 66size code. The average apparel size piteh measurement distributions(bust girth and hip girth respectively) of young group are 9cm and 13cm in 55 size code, those of missy group are 7 em and 3 cm in 66 size code, and those of madame group are 6cm and 4cm in 77 size code. The ease of bust girth and hip girth in missy group are much more than other groups.

• Journal of KIISE:Software and Applications
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• v.32 no.3
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• pp.227-235
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• 2005

In the embedded system domain, both memory requirement and energy consumption are great concerns. To save memory and energy, the 32 bit ARM processor supports the 16 bit Thumb instruction set. For a given program, the Thumb code is typically smaller than the ARM code. However, the limitations of the Thumb instruction set can often lead to generation of poorer quality code. To generate codes with smaller size but a little slower execution speed, Krishnaswarmy suggests a profiling guided selection algorithm at module level for generating mixed ARM and Thumb codes for application programs. The resulting codes of the algorithm give significant code size reductions with a little loss in performance. When the instruction set is selected at module level, some functions, which should be compiled in Thumb mode to reduce code size, are compiled to ARM code. It means we have additional code size reduction chance. In this paper, we propose a profile guided selection algorithm at function level for generating mixed ARM and Thumb codes for application programs so that the resulting codes give additional code size reductions without loss in performance compared to the module level algorithm. We can reduce 2.7％ code size additionally with no performance penalty

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.48 no.12
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• pp.1575-1579
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• 1999

Embedded processors often accommodate two instruction sets, a standard instruction set and a compressed instruction set. With the compressed instruction set, code size can be reduced while instruction count (and consequently execution time) can be increased. To achieve code size reduction without significant increase of execution time, this paper proposes a new compressed instruction set architecture, called TOE (Two Operations Execution). The proposed instruction set format includes the parallel bit that indicates an instruction can be executed simultaneously with the next instruction. To add the parallel bit, TOE instruction format reduces the destination register field. The reduction of the register field limits the number of registers that are accessible by an instruction. To overcome the limited accessibility of registers, TOE adapts non-homogeneous register partition in which registers are divided into multiple subsets, each of which are accessed by different groups of instructions. With non-homogeneous registers, each instruction can access only a limited number of registers, but an entire program can access all available registers. With efficient non-homogeneous register allocator, all registers can be used in a balanced manner. As a result, the increase of code size due to register spills is negligible. Experimental results show that more than 30% of TOE instructions can be executed in parallel without significant increase of code size when compared to existing Thumb instruction set.

• Journal of KIISE:Software and Applications
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• v.32 no.8
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• pp.819-833
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• 2005

Code size reduction is ever becoming more important for compilers targeting embedded processors because these processors are often severely limited by storage constraints and thus the reduced code size can have a positively significant Impact on their performance. Various code size reduction techniques have different motivations and a variety of application contexts utilizing special hardware features of their target processors. In this work, we propose a novel technique that fully utilizes a set of hardware instructions, called the multiple load/store (MLS), that are specially featured for reducing code size by minimizing the number of memory operations in the code. To take advantage of this feature, many microprocessors support the MLS instructions, whereas no existing compilers fully exploit the potential benefit of these instructions but only use them for some limited cases. This is mainly because optimizing memory accesses with MLS instructions for general cases is an NP-hard problem that necessitates complex assignments of registers and memory off-sets for variables in a stack frame. Our technique uses a couple of heuristics to efficiently handle this problem in a polynomial time bound.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.7
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• pp.1427-1436
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• 1997

Turbo codes, decoded through an iterative decoding algorithm, habe recently been shown to yidel remarkable coding gains close to theoretical limits in the Gaussian channel environment. This thesis presents the performance of Turbo code through the computer simulation. The performance of modified Turbo code is compared to that of the conventional Turbo codes. The modified Turbo code reduces the time delay in decoding with minimal effect to the performance for voice transmission sytems. To achieve the same performance, random interleaver the size of which is no less than the square root of the original one should be used. Also, the modified Turbo code is applied to MC-CDMA system, and its performance is analyzed under the Rayleigh Fading channel environment. In Rayleigh fading channel environment, due to the amplitude distortion caused by fading, the interleaver of the size twice no less than that in the Gaussian channel enironment was required. In overall, the modified Turbo code maintained the performance of the conventional Turbo code while the time delay in transmission and decoding was reduced at the rate of multiples of two times the squared root of the interleaver size.

• Nuclear Engineering and Technology
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• v.54 no.6
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• pp.2077-2083
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• 2022

In the unlikely event of core disruptive accident in sodium cooled fast reactors, the reactor containment building would be bottled up with sodium and fission product aerosols. The behavior of these aerosols is crucial to estimate the in-containment source term as a part of nuclear reactor safety analysis. In this work, the evolution of sodium aerosol characteristics (mass concentration and size) is simulated using HAARM-S code. The code is based on the method of moments to solve the integro-differential equation. The code is updated to FORTRAN-77 and run in Microsoft FORTRAN PowerStation 4.0 (on Desktop). The sodium aerosol characteristics simulated by HAARM-S code are compared with the measured values at Aerosol Test Facility. The maximum deviation between measured and simulated mass concentrations is 30% at initial period (up to 60 min) and around 50% in the later period. In addition, the influence of humidity on aerosol size growth for two different aerosol mass concentrations is studied. The measured and simulated growth factors of aerosol size (ratio of saturated size to initial size) are found to be matched at reasonable extent. Since sodium is highly reactive with atmospheric constituents, the aerosol growth factor depends on the hygroscopic growth, chemical transformation and density variations besides coagulation. Further, there is a scope for the improvement of the code to estimate the aerosol dynamics in confined environment.

• Journal of Convergence for Information Technology
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• v.9 no.2
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• pp.85-93
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• 2019

There is currently no recognized standard for the size of lifts. Each elevator manufacturer sets the maximum allowable floor area that meets the capacity calculation standard of the elevator using the maximum used car floor area, which is defined by EN-CODE and the domestic inspection standard, and determines the elevator size based on their own standards. In this paper, we propose a method to more easily determine the elevator size. To do this, we implemented a program that calculates the size of the elevator by inputting the dimensions of the hoistway. This program will be useful method for quick decision making and elevator installation considering the elevator factors according to the already determined hoistway size of the building and calculating the EN-CODE currently used and the size of the elevator according to domestic inspection standards.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.112-115
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• 2009

PI code searching method of RDS(Radio Data System) are unique method of maintain desired channel on moving machine like vehicle. Efficient and fast PI code search method are researching on the all of RDS related systems for both find more better channel before Original channel signal go to bad and find desired good signal quickly when get out of Weak signal Area. But Embedded system has limited environment like memory size, so It is very difficult to apply many well known PI code searching method. This thesis suggests simple and effective method of searching PI code, considering a Embedded System Environment.

• Journal of KIISE
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• v.43 no.1
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• pp.34-39
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• 2016

JavaScript is widely used in web pages with HTML. Many JavaScript engines adopt Just-in-time compilers to accelerate the execution of JavaScript programs. Recently, many newly introduced devices are adopting 64-bit CPUs instead of 32-bit and Just-in-time compilers for 64-bit CPU are slowly being introduced in JavaScript engines. However, there are many inefficiencies in the currently available Just-in-time compilers for 64-bit devices. Especially, the size of code is significantly increased compared to 32-bit devices, mainly due to 64-bit wide addresses in 64-bit devices. In this paper, we are going to address the inefficiencies introduced by 64-bit wide addresses and values in the Just-in-time compiler for the V8 JavaScript engine and propose more efficient ways of generating constant values and addresses to reduce the size of code. We implemented the proposed optimization in the V8 JavaScript engine and measured the size of code as well as performance improvements with Octane and SunSpider benchmarks. We observed a 3.6% performance gain and 0.7% code size reduction in Octane and a 0.32% performance gain and 2.8% code size reduction in SunSpider.

• Journal of Biomedical Engineering Research
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• v.15 no.1
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• pp.83-88
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• 1994

The transform trellis code is an optimal source code as a block size and the constraint length of a shift register go to infinite for stationary Gaussian sources with the squared-error distortion measure. However to implement this code, we have to choose the finite block size and constraint length. Moreover real-world sources are inherently non stationary. To overcome these difficulties, we developed a training algorithm for the transform trellis code. The trained transform trellis code which uses the same rates to each block led to a variation in the resulting distortion from one block to another. To alleviate this non-uniformity in the encoded image, we constructed clusters from the variance of the training data and assigned different rates for each cluster.