• Journal of Power Electronics
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• v.9 no.3
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• pp.365-376
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• 2009

In this paper, the implementation of a three-phase shunt active power filter is presented. The filter is essentially three independent single-phase current-controlled voltage source inverters (CC-VSI) with a common DC bus. The CC- VSI is operated to directly control the AC grid current to be sinusoidal and in phase with the grid voltage without detecting the load currents. The APF consists of a current control loop, which shapes the grid currents to be sinusoidal and a voltage control loop, which regulates the active power balance of the system. The experimental results indicate that the active filter is able to handle predominantly the harmonics, as well as the unbalance and reactive power, so that the grid currents are sinusoidal, in phase with the grid voltages and symmetrical.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.28 no.1
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• pp.96-104
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• 2014

The all pass filter generates a virtual q-axis voltage component with $90^{\circ}$ phase delay but the virtual q-axis voltage cannot detect the voltage depending on the phase of the grid voltage. To overcome the problem, q-axis voltage component is generated from difference between the current and previous value of d-axis voltage component in the stationary reference frame. However, the difference voltage between the current and previous value around the zero crossing voltage is not enough to detect the voltage sag. Therefore, the new detection scheme which can detect the sag around the zero crossing voltage is proposed.

• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.104-106
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• 2018

The harmonics and the DC offset in the grid can cause serious synchronization problems for grid connected inverters (GCIs) which leads not able to satisfy the IEEE 519 and p1547 standards in terms of phase and frequency variations. In order to guarantee the smooth and reliable synchronization of GCIs with the grid, Phase Locked Loop (PLL) is the crucial element. Typically, the performance of the PLL is assessed to limit the grid disturbances e.g. grid harmonics, DC Offset and voltage sag etc. To ensure the quality of GCI, the PLL should be precise in estimating the grid amplitude, frequency and phase. Therefore, in this paper a novel Robust PLL technique called Digital Lock-in Amplifier (DLA) PLL is proposed. The proposed PLL estimate the frequency variations and phase errors accurately even in the highly distorted grid voltage conditions like grid voltage harmonics, DC offsets and grid voltage sag. To verify the performance of proposed method, it is compared with other six conventional used PLLs (CCF PLL, SOGI PLL, SOGI LPF PLL, APF PLL, dqDSC PLL, MAF PLL). The comparison is done by simulations on MATLAB Simulink. Finally, the experimental results are verified with Single Phase GCI Prototype.

• The Transactions of the Korean Institute of Power Electronics
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• v.5 no.4
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• pp.335-342
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• 2000

A new control method for a single-phase active power filter, based on a load current estimation using a DC capacitor voltage of active power filter without sensing nonlinear load current, is proposed in this paper. Because the method proposed can remove the load current sensor in comparison with a conventional method sensing the load current and DC capacitor voltage together, it can make the active power filter easy installation, low cost, small size with no performance detriment. In addition, sample-hold technique and proportional control method is adopted to control the DC capacitor voltage and as no delay element such as LPF or PI control in the conventional method is used, the transient response is fast and good. Operation of a single-phase active power filter which consist of eight mode is explained according to utility voltage, compensation current and switch state, and compensation characteristics of active power filter using proposed method is verified by experiment.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.819-822
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• 1998

A new active power filter (APF) circuit with a current compesation estimation method is proposed. The current compensation estimation method replaces a current sensor with an estimating circuit and therefore reduces the implementation cost In addition, a simple control scheme, based on the energy balance concept, is adopted to control the voltage of a DC capacitor. Therefore energy change in the DC capacitor can be compensanted in the next cycle. Since a sampling technique is used, a larger DC capacitor voltage ripple can be permissible and a relatively smaller DC capacitor can be used. The proposed method has advantages of the reduction of one current sensor, low implementation cost, and fast transient responses. The theoretical analysis and simulation results are given. The proposed control method is successfully verified by computer simulation.

• Proceedings of the KIPE Conference
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• 2003.07a
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• pp.208-211
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• 2003

본 논문에서는 비선형 단상부하에 의해 발생하는 전류 고조파를 보상하기 위한 단상능동전력필터의 제어방법을 제안한다. 측정된 부하전류에 시간지연을 주어 가상의 두 번째 상을 만들어서 단상시스템을 두 축을 갖는 시스템으로 만들어 복소계산이 가능하게 한다 기존의 방법과 달리 저역통과필터의 지연특성을 고려하여 필터를 통과한 지연된 위상을 가진 정현파를 가상의 상으로 이용하였다 두 개 의상이 존재하므로 순시로 무효전력을 구할 수 있게된다. 본 논문에서는 회전좌표계를 사용하여 순시계산을 하였고, 부하전류만을 검출하여 보상전류 지령치를 구하였다. RL부하에 대한 실험을 수행하였고, 이러한 실험을 통하여 제안된 제어법의 유효성을 입증하였다.

• Proceedings of the KIPE Conference
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• 2018.07a
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• pp.150-152
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• 2018

계통 사고 시 계통연계형 인버터에 대한 각국의 계통 규정(Grid Code)이 더욱 엄격해 지고 있다. 계통 규정은 특히, 계통 내 저전압 사고로 인한 인버터 운전계속성(Low Voltage Ride Through, LVRT)뿐만 아니라 0 전압 사고 시 운전계속성(Zero Voltage Ride Through, ZVRT)을 통해 인버터가 계통 안정화에 기여할 것을 요구하고 있다. 계통연계형 인버터는 계통전압과 인버터 출력 위상을 일치시키는 PLL제어가 적용되며 본 논문에서는 위상 추종이 어려운 0 전압 상황에서도 안정적인 위상 추종 및 인버터 출력이 가능한 PLL 방법을 제안한다. 단상 인버터에 Notch filter-PLL, APF를 이용한 dq-PLL, 및 SOGI-PLL(Second-order Generalized Intergrator)을 적용하고 독일, 미국, 및 일본의 0 전압 상황에 대해 시뮬레이션과 실험을 진행하여 제안한 PLL 기법의 ZVRT 유효성을 확인하였다.

• Journal of Electrical Engineering and Technology
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• v.13 no.2
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• pp.711-721
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• 2018

This paper presents a single-phase asymmetric half-bridge cascaded multilevel inverter based series active power filter (SAPF) for harmonic voltage compensation. The effect of level number on performance of the proposed SAPF is examined in terms of total harmonic distortion (THD) and system efficiency. Besides, the relationship between the level number and the number of switching device are compared with the other multilevel inverter topologies used in APF applications. The paper is also aimed to demonstrate the capability of the SAPF for compensating harmonic voltages alone, without using a passive power filter (PPF). To obtain the required output voltage, a new switching algorithm is developed. The proposed SAPF with levels of 7, 15 and 31 is used in both simulation and experimental studies and the harmonic voltages of the load connected to the point of common coupling (PCC) is compensated under two different loading conditions. Furthermore, very high system efficiency values such as 98.74% and 96.84% are measured in the experimental studies and all THD values are brought into compliance with the IEEE-519 Standard. As a result, by increasing the level number of the inverter, lower THD values can be obtained even under high harmonic distortion levels while system efficiency almost remains the same.