• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.31-33
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• 2007

Devising an efficient one-pass frequent pattern mining algorithm has been an issue in data mining research in recent past. Pattern growth algorithms like FP-Growth which are found more efficient than candidate generation and test algorithms still require two database scans. Moreover, FP-growth approach requires rebuilding the base-tree while mining with different support counts. In this paper we propose an item-based tree, called I-Tree that not only efficiently mines frequent patterns with single database scan but also provides multiple mining scopes with multiple support thresholds. The 'build-once-mine-many' property of I-Tree allows it to construct the tree only once and perform mining operation several times with the variation of support count values.

• Journal of Korea Spatial Information System Society
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• v.11 no.1
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• pp.127-136
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• 2009

This paper proposes an on-line mining algorithm of moving trajectory patterns in RFID data streams considering changing characteristics over time and constraints of single-pass data scan. Since RFID, sensor, and mobile network technology have been rapidly developed, many researchers have been recently focused on the study of real-time data gathering from real-world and mining the useful patterns from them. Previous researches for sequential patterns or moving trajectory patterns based on stream data have an extremely time-consum ing problem because of multi-pass database scan and tree traversal, and they also did not consider the time-changing characteristics of stream data. The proposed method preserves the sequential strength of 2-lengths frequent patterns in binary relationship table using the time-evolving graph to exactly reflect changes of RFID data stream from time to time. In addition, in order to solve the problem of the repetitive data scans, the proposed algorithm infers candidate k-lengths moving trajectory patterns beforehand at a time point t, and then extracts the patterns after screening the candidate patterns by only one-pass at a time point t+1. Through the experiment, the proposed method shows the superior performance in respect of time and space complexity than the Apriori-like method according as the reduction ratio of candidate sets is about 7 percent.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.3
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• pp.693-698
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• 2018

This paper proposes a vehicle detection method for parking areas using unmanned aerial vehicles (UAVs) and using YOLOv2, which is a recent, known, fast, object-detection real-time algorithm. The YOLOv2 convolutional network algorithm can calculate the probability of each class in an entire image with a one-pass evaluation, and can also predict the location of bounding boxes. It has the advantage of very fast, easy, and optimized-at-detection performance, because the object detection process has a single network. The sliding windows methods and region-based convolutional neural network series detection algorithms use a lot of region proposals and take too much calculation time for each class. So these algorithms have a disadvantage in real-time applications. This research uses the YOLOv2 algorithm to overcome the disadvantage that previous algorithms have in real-time processing problems. Using Darknet, OpenCV, and the Compute Unified Device Architecture as open sources for object detection. a deep learning server is used for the learning and detecting process with each car. In the experiment results, the algorithm could detect cars in a dense area using UAVs, and reduced overhead for object detection. It could be applied in real time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.115-124
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• 2004

This paper proposes a high efficient and low power FIR filter chip for partial-response maximum likelihood (PRML) disk drive read channels; it is a 6-bit, 8-tap digital FIR filter. The proposed filter employs a parallel processing architecture and consists of 4 pipeline stages. It uses the modified Booth algorithm for multiplication and compressor logic for addition. CMOS pass-transistor logic is used for low power consumption and single-rail logic is used to reduce the chip area. The proposed filter is actually implemented and the chip dissipates 120mV at 100MHz, uses a 3.3V power supply and occupies 1.88 ${\times}$ 1.38 $\textrm{mm}^2$. The implemented filter requires approximately 11.7% less power compared with the existing architectures that use the similar technology.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.40 no.4
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• pp.227-236
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• 2003

This paper proposes a modified jointly-blue noise mask (MJBNM) method using the S-CIELAB color measure as digital color halftoning method. Based on an investigation of the relation between the pattern visibility and the chromatic error, of a blue noise pattern, a halftoning method is proposed that reduces the chromatic error, while preserving a high quality blue noise pattern. Accordingly, to reduce the chrominance error, the low-pass filtered error and S-CIELAB chrominance error are both considered during the mask generation procedure and calculated for single and combined patterns. Using the calculated low-pass filtered error, the patterns are then updated by either adding or removing dots from the multiple binary patterns. Finally, the pattern exhibiting the lower S-CIELAB chrominance error is selected. Experimental results demonstrated that the proposed algorithm can produce a visually pleasing half toned image with a lower chrominance error than the JBNM method.

• Journal of the Korea Society of Computer and Information
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• v.11 no.3
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• pp.141-149
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• 2006

In this paper, we introduce an improved algorithm for computing matrix triple product that commonly arises in primal-dual optimization method. In computing $P=AHA^{t}$, we devise a single pass algorithm that exploits the block diagonal structure of the matrix H. This one-phase scheme requires fewer floating point operations and roughly half the memory of the generic two-phase algorithm, where the product is computed in two steps, computing first $Q=HA^{t}$ and then P=AQ. The one-phase scheme achieved speed-up of 2.04 on Intel Itanium II platform over the two-phase scheme. Based on memory latency and modeled cache miss rates, the performance improvement was evaluated through performance modeling. Our research has impact on performance tuning study of complex sparse matrix operations, while most of the previous work focused on performance tuning of basic operations.

• The KIPS Transactions:PartA
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• v.8A no.2
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• pp.157-166
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• 2001

A simulation package has been developed as an event-driven system that can handle the hardware configuration of STC104 and algorithm proposed in the sister paper of ‘Study on High Speed Routers(II).’After various STC104 topology of meshes, torus, and hypercubes are constructed using up to 512 switches, the performance of each topology has been analyzed under different message generation rate in terms of throughputs, latency, and packet blocking time. Modified multicast algorithms for STC104 have been proposed for STC104 after U-mesh and U-torus in order to overcome the multicasting difficulty because of the point-to-point communication method found in STC104. The performance of the multicast algorithms have been analyzed over meshes and torus configuration. Throughput gets higher in the order of mesh, torus, and hypercube. Throughput difference among topology were distinctive in the zone of high message generation rate. Latency and blocking time increased in the order of hypercube, torus, and mesh. U-mesh and U-torus of software multicast showed similar throughput, however, U-mesh peformed slightly better result. These algorithms showed eight to ten times better results compared to individual message pass for 90 destination nodes. Multi-link environment also showed better performance than single-link environment because multi-link network used the extra links for communication.

• Journal of Astronomy and Space Sciences
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• v.38 no.2
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• pp.105-117
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• 2021

In this study, a preliminary trajectory design is conducted for a conceptual spacecraft mission to a near-Earth asteroid (NEA) (99942) Apophis, which is expected to pass by Earth merely 32,000 km from the Earth's surface in 2029. This close approach event will provide us with a unique opportunity to study changes induced in asteroids during close approaches to massive bodies, as well as the general properties of NEAs. The conceptual mission is set to arrive at and rendezvous with Apophis in 2028 for an advanced study of the asteroid, and some near-optimal (in terms of fuel consumption) trajectories under this mission architecture are to be investigated using a global optimization algorithm called monotonic basin hopping. It is shown that trajectories with a single swing-by from Venus or Earth, or even simpler ones without gravity assist, are the most feasible. In addition, launch opportunities in 2029 yield another possible strategy of leaving Earth around the 2029 close approach event and simply following the asteroid thereafter, which may be an alternative fuel-efficient option that can be adopted if advanced studies of Apophis are not required.

• The Transactions of the Korea Information Processing Society
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• v.4 no.1
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• pp.311-323
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• 1997

This paper presents a fast fault simulation system for detecting stuck-at faults in mixed-level combinational logic circuits with gale level and switch -level primitives. For a practical fault simulator, the types are not restricted to static switch-level and/or gate-level circuits, but include dynamic switch-level circuits. To efficiently handle the multiple signal contention problems at wired logic elements, we propose a six-valued logic system and its logic calculus which are used together with signal strength information. As a basic algorithm for the fault simulation process, a well -known gate-level parallel pattern single fault propagation(PPSFP) technique is extended to switch-level circuits in order to handle pass-transistor circuits and precharged logic circuits as well as static CMOS circuits. Finally, we demonstrate the efficiency of our system through the experimental results for switch-level ISCAS85 benchmark combinational circuits and various industrial mixed-level circuits.

• The Transactions of the Korean Institute of Power Electronics
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• v.25 no.2
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• pp.73-78
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• 2020

In this study, a novel reactive power control scheme is proposed to supply stable reactive power to the distribution line by compensating a ripple voltage of DC link. In a single-phase system, a magnitude of second harmonic is inevitably generated in the DC link voltage, and this phenomenon is further increased when the capacity of DC link capacitor decreases. Reactive power control was performed by controlling the d-axis current in the virtual synchronous reference frame, and the voltage control for maintaining the DC link voltage was implemented through the q-axis current control. The proposed method for compensating the ripple voltage was classified into three parts, which consist of the extraction unit of DC link voltage, high pass filter (HPF), and time delay unit. HPF removes an offset component of DC link voltage extracted from integral, and a time delay unit compensates the phase leading effect due to the HPF. The compensated DC voltage is used as feedback component of voltage control loop to supply stable reactive power. The performance of the proposed algorithm was verified through simulation and experiments. At DC link capacitance of 375 uF, the magnitude of ripple voltage decreased to 8 Vpp from 74 Vpp in the voltage control loop, and the total harmonic distortion of the current was improved.