• JSTS:Journal of Semiconductor Technology and Science
• /
• v.10 no.2
• /
• pp.143-151
• /
• 2010

In this work, we propose a single electron memory 'SEM' design which consist of two key blocs: A memory bloc, with a voltage source $V_{Mem}$, a pure capacitor connected to a tunnel junction through a metallic memory node coupled to the second bloc which is a Single Electron Transistor "SET" through a coupling capacitance. The "SET" detects the potential variation of the memory node by the injection of electrons one by one in which the drainsource current is presented during the memory charge and discharge phases. We verify the design of the SET/SEM cell by the SIMON tool. Finally, we have developed a MAPLE code to predict the retention time and nonvolatility of various SEM structures with a wide operating temperature range.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2006.05a
• /
• pp.894-897
• /
• 2006

Spatial distribution of injected electrons and holes is evaluated by using single-junction charge pumping technique in SONOS(Poly-silicon/Oxide/Nitride/Oxide/Silicon) memory cells. Injected electron are limited to length of ONO(Oxide/Nitride/oxide) region in locally ONO stacked cell, while are spread widely along with channel in fully ONO stacked cell. Hot-holes are trapped into the oxide as well as the ONO stack in locally ONO stacked cell.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.1 no.1
• /
• pp.40-49
• /
• 2001

We have developed a repeatable process of forming uniform, small-size and high-density self-assembled Si nano-crystals. The Si nano-crystals were fabricated in a conventional LPCVD (low pressure chemical vapor deposition) reactor at $620^{\circ}c$ for 15 sec. The nano-crystals were spherical shaped with about 4.5 nm in diameter and density of $5{\times}l0^{11}/$\textrm{cm}^2$. More uniform dots were fabricated on nitride film than on oxide film. To take advantage of the above-mentioned characteristics of nitride film while keeping the high interface quality between the tunneling dielectrics and the Si substrate, nitride-oxide tunneling dielectrics is proposed in n-channel device. For the first time, the single electron effect at room temperature, which shows a saturation of threshold voltage in a range of gate voltages with a periodicity of ${\Delta}Ｖ_{GS}\;{\approx}\;1.7{\;}V$, corresponding to single and multiple electron storage is reported. The feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. The programming mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.31-32
• /
• 2010

In our previous reports [1-3], electron transport for the switching and memory devices using alkyl thiol-tethered Ru-terpyridine complex compounds with metal-insulator-metal crossbar structure has been presented. On the other hand, among organic memory devices, a memory based on the OFET is attractive because of its nondestructive readout and single transistor applications. Several attempts at nonvolatile organic memories involve electrets, which are chargeable dielectrics. However, these devices still do not sufficiently satisfy the criteria demanded in order to compete with other types of memory devices, and the electrets are generally limited to polymer materials. Until now, there is no report on nonvolatile organic electrets using nano-interfaced organic monomer layer as a dielectric material even though the use of organic monomer materials become important for the development of molecularly interfaced memory and logic elements. Furthermore, to increase a retention time for the nonvolatile organic memory device as well as to understand an intrinsic memory property, a molecular design of the organic materials is also getting important issue. In this presentation, we report on the OFET memory device built on a silicon wafer and based on films of pentacene and a SiO2 gate insulator that are separated by organic molecules which act as a gate dielectric. We proposed push-pull organic molecules (PPOM) containing triarylamine asan electron donating group (EDG), thiophene as a spacer, and malononitrile as an electron withdrawing group (EWG). The PPOM were designed to control charge transport by differences of the dihedral angles induced by a steric hindrance effect of side chainswithin the molecules. Therefore, we expect that these PPOM with potential energy barrier can save the charges which are transported to the nano-interface between the semiconductor and organic molecules used as the dielectrics. Finally, we also expect that the charges can be contributed to the memory capacity of the memory OFET device.[4]

• Proceedings of the Korean Vacuum Society Conference
• /
• 2011.02a
• /
• pp.27-27
• /
• 2011

For the design of real applicable molecular devices, current-voltage properties through molecular nanostructures such as metal-molecule-metal junctions (molecular junctions) have been studied extensively. In thiolate monolayers on the gold electrode, the chemical bonding of sulfur to gold and the van der Waals interactions between the alkyl chains of neighboring molecules are important factors in the formation of well-defined monolayers and in the control of the electron transport rate. Charge transport through the molecular junctions depends significantly on the energy levels of molecules relative to the Fermi levels of the contacts and the electronic structure of the molecule. It is important to understand the interfacial electron transport in accordance with the increased film thickness of alkyl chains that are known as an insulating layer, but are required for molecular device fabrication. Thiol-tethered RuII terpyridine complexes were synthesized for a voltage-driven molecular switch and used to understand the switch-on mechanism of the molecular switches of single metal complexes in the solid-state molecular junction in a vacuum. Electrochemical voltammetry and current-voltage (I-V) characteristics are measured to elucidate electron transport processes in the bistable conducting states of single molecular junctions of a molecular switch, Ru(II) terpyridine complexes. (1) On the basis of the Ru-centered electrochemical reaction data, the electron transport rate increases in the mixed self-assembled monolayer (SAM) of Ru(II) terpyridine complexes, indicating strong electronic coupling between the redox center and the substrate, along the molecules. (2) In a low-conducting state before switch-on, I-V characteristics are fitted to a direct tunneling model, and the estimated tunneling decay constant across the Ru(II) terpyridine complex is found to be smaller than that of alkanethiol. (3) The threshold voltages for the switch-on from low- to high-conducting states are identical, corresponding to the electron affinity of the molecules. (4) A high-conducting state after switch-on remains in the reverse voltage sweep, and a linear relationship of the current to the voltage is obtained. These results reveal electron transport paths via the redox centers of the Ru(II) terpyridine complexes, a molecular switch.

• Transactions on Electrical and Electronic Materials
• /
• v.4 no.4
• /
• pp.26-29
• /
• 2003

To discover electrical properties of individual single wall nanotube(SWNT), a number of SWNT-based tubeFETs have been fabricated. The device consists of a single semiconducting SWNT on an insulating substrate, contacted at each end by metal electrodes. It presents high transconductances, and charge storage phenomenon, which is the operations of injecting electrons from the nanotube channel of a tubeFET into charge traps on the surface of the $SiO_2$ gate dielectric, thus shifting the threshold voltage. This phenomenon can be repeated many times, and maintained for the hundreds of seconds at room temperature. We will report this phenomenon as the memory effects of the SWNT, and attempt to use this property for the memory device.

• Journal of information and communication convergence engineering
• /
• v.4 no.2
• /
• pp.84-87
• /
• 2006

Lateral distributions of locally injected electrons and holes in an oxide-nitride-oxide (ONO) dielectric stack of two different silicon-oxide-nitride-oxide-silicon (SONOS) memory cells are evaluated by single-junction charge pumping technique. Spatial distribution of electrons injected by channel hot electron (CHE) for programming is limited to length of the ONO region in a locally ONO stacked cell, while is spread widely along with channel in a fully ONO stacked cell. Hot-holes generated by band-to-band tunneling for erasing are trapped into the oxide as well as the ONO stack in the locally ONO stacked cell.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.07a
• /
• pp.54-57
• /
• 2002

In this study, a new programming method, to minimize the generation of Si-SiO$_2$ interface traps of scaled SONOS flash memory as a function of number of program/erase cycles has been proposed. In the proposed programming method, power supply voltage is applied to the gate, forward biased program voltage is applied to the source and the drain, while the substrate is left open, so that the program is achieved by Modified Fowler-Nordheim (MFN) tunneling of electron through the tunnel oxide over source and drain region. For the channel erase, erase voltage is applied to the gate, power supply voltage is applied to the substrate, and the source and drain are open. A single power supply operation of 3 V and a high endurance of 1${\times}$10$\^$6/ prograss/erase cycles can be realized by the proposed programming method. The asymmetric mode in which the program voltage is higher than the erase voltage, is more efficient than symmetric mode in order to minimize the degradation characteristics of scaled SONOS devices because electrical stress applied to the Si-SiO$_2$ interface is reduced by short programming time.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.11a
• /
• pp.35-38
• /
• 2002

In this paper, the characteristics of channel hot electron (CHE) injection for the write operation in a NOR-type SONOS flash memory with common source line were investigated. The thicknesses of he tunnel oxide, the memory nitride， and the blocking oxide layers for the gate insulator of the fabricated SONOS devices were $34{\AA}$, $73{\AA}$, and $34{\AA}$, respectively. The SONOS devices compared to floating gate devices have many advantages, which are a simpler cell structure, compatibility with conventional logic CMOS process and a superior scalability. For these reasons, the introduction of SONOS device has stimulated. In the conventional SONOS devices, Modified Folwer-Nordheim (MFN) tunneling and CHE injection for writing require high voltages, which are typically in the range of 9 V to 15 V. However CHE injection in our devices was achieved with the single power supply of 5 V. To demonstrate CHE injection, substrate current (Isub) and one-shot programming curve were investigated. The memory window of about 3.2 V and the write speed of $100{\mu}s$ were obtained. Also, the disturbance and drain turn-on leakage during CHE injection were not affected in the SONOS array. These results show that CHE injection can be achieved with a low voltage and single power supply, and applied for the high speed program of the SONOS memory devices.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.240-240
• /
• 2010

A multiple alloy metal nano-dots memory using FN tunneling was investigated in order to confirm its structural possibility for future flash memory. In this work, a multiple FePt nano-dots device with a high work function (~5.2 eV) and extremely high dot density (${\sim}\;1.2{\times}10^{13}/cm^2$) was fabricated. Its structural effect for multiple layers was evaluated and compared to one with a single layer in terms of the cell characteristics and reliability. We confirm that MOS capacitor structures with 2-4 multiple FePt nano-dot layers provide a larger threshold voltage window and better retention characteristics. Furthermore, it was also revealed that several process parameters for block oxide and inter-tunnel oxide between the nano-dot layers are very important to improve the efficiency of electron injection into multiple nano-dots. From these results, it is expected that a multiple FePt nano-dots memory using Fowler-Nordheim (FN)-tunneling could be a candidate structure for future flash memory.