• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.28-33
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• 2006

An integrated 3.125Gbps clock and data recovery (CDR) circuit is presented. The circuit does not need a reference clock. It has a phase and frequency detector (PFD), which incorporates a bang-bang type 4X oversampling PD and a rotational frequency detector (FD). It also has a ring oscillator type VCO with four delay stages and three zero-offset charge pumps. With a proposed PD and m, the tracking range of 24% can be achieved. Experimental results show that the circuit is capable of recovering clock and data at rates of 3.125Gbps with 0.18 um CMOS technology. The measured recovered clock jitter (p-p) is about 14ps. The CDR has 1.8volt single power supply. The power dissipation is about 140mW.

• Transactions on Semiconductor Engineering
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• v.2 no.3
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• pp.1-5
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• 2024

This paper presents a crystal-less reference clock recovery (CR) frequency synthesizer with compensation designed for Bluetooth Low Energy (BLE) Smart-tag applications, operating at frequencies of 32, 72, and 80MHz. In contrast to conventional frequency synthesizers, the proposed design eliminates the need for external components. Using a single-ended antenna to receive a minimal input power of -36dBm at a 2.4GHz signal, the CR synthesizes frequencies by processing the RF signal received through a Low Noise Amplifier ( L N A ) . This approach allows the system to generate a reference clock without relying on a crystal. The received signal is amplified by the LNA and then input to a 16-bit ACC (Automatic Clock Compensation) circuit. The ACC compares the frequency of the received signal with the oscillator output signal, using the synthesis of a 32MHz reference clock through a frequency compensation method. The oscillator is constructed using a Ring Oscillator (RO) with a Frequency Divider, offering three different frequencies (32/72/80MHz) for various system components. The proposed frequency synthesizer is implemented using a 55-nm CMOS process.

• Journal of Positioning, Navigation, and Timing
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• v.10 no.3
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• pp.159-168
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• 2021

Precise Point Positioning-Real Time Kinematic (PPP-RTK) is an improved PPP method that provides the user receiver with satellite code and phase bias correction information in addition to the satellite orbit and clock, thus enabling single-receiver ambiguity resolution. Single station PPP-RTK concept is special case of PPP-RTK in that corrections are computed, instead of a network, by only one single GNSS receiver. This study is performed to experimentally verify the positioning accuracy performance of single baseline RTK level by a user who utilizes correction for a single station PPP-RTK using dual frequencies. As an experimental result, the horizontal and vertical 95% accuracy was 2.2 cm, 4.4 cm, respectively, which verify the same performance as the single baseline RTK.

• Journal of Life Science
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• v.25 no.11
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• pp.1304-1310
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• 2015

The period circadian clock gene 3 (PER3) plays a role in the mammalian circadian clocksystem. A regular exercise regime may affect the PER3 transcription in skeletal muscle. Although the effects of day length on circadian and circannual processes are well established in humans and mice, the influence of exercise on these processes in the horse has not been investigated. The present study investigated the expression of the PER3 gene following exercise in a thoroughbred breed of Korean horse. In addition, a comprehensive in silico nonsynonymous single nucleotide polymorphism (nsSNP) analysis of the horse PER3 gene and predicted effects of nsSNPs on proteins were examined. The expression of PER3 in skeletal muscle was significantly upregulated after exercise. Four nsSNPs were functionally annotated and analyzed by computational prediction. The total free energy and RMSD values of PER3 gene showed causative mutations. The results showed that nsSNP s395916798 (G72R) was associated with residues that have stabilizing effects on structure and function of PER3 gene. This study documented role of PER3 gene in phenotypic adaptation related to exercise in skeletal muscle. Further, the SNPs in PER3 could serve as useful biomarkers of early recovery after exercise in racehorses.

• Journal of the Korean Professional Engineers Association
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• v.33 no.4
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• pp.53-58
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• 2000

Within 10years, it will be possible to integrate 10B transistors on a single chip microprocessor which wilt operate far beyond GHZ, and it will execute about 20-200 instructions per clock cycle from widely variable instruction streams leveraging SMT(Simultaneous Multithreading) technology . Also it will decouple the current legacy X86 binary compatibility by translation layer such as code morphing technology.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.3
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• pp.67-78
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• 2013

In this paper, We proposed an development method of application framework for using the precision time protocol(PTP) based on physical layer devices to synchronize clocks across a network with IEEE1588 capable devices. The algorithm was not designed as a complete solution across all conditions, but is intended to show the feasibility of such a for the PTP(Precision Time Protocol) based on time synchronization of heterogeneous network between devices that support in IEEE 1588 Standard application framework. With synchronization messages per second, the system was able to accurately synchronize across a single heavily loaded switch. we describes a method of synchronization that provides much more accurate synchronization in systems with larger networks. In this paper, using the IEEE 1588 PTP support for object-oriented modeling techniques through the 'application framework development Development(AFDM)' is proposed. The method described attempts to detect minimum delays, or precision packet probe and packet metrics. The method also takes advantage of the Tablet PC(Primary to Secondary) clock control mechanism to separately control clock rate and time corrections, minimizing overshoot or wild swings in the accuracy of the clock. We verifying the performance of PTP Systems through experiments that proposed method.

• ETRI Journal
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• v.42 no.4
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• pp.480-490
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• 2020

More than 42 000 fires occur nationwide and cause over 2500 casualties every year. There is a lack of specialized equipment, and rescue operations are conducted with a minimal number of apparatuses. Through-the-wall radars (TTWRs) can improve the rescue efficiency, particularly under limited visibility due to smoke, walls, and collapsed debris. To overcome detection challenges and maintain a small-form factor, a TTWR system-on-chip (SoC) and its architecture have been proposed. Additive reception based on coherent clocks and reconfigurability can fulfill the TTWR demands. A clock-based single-chip infrared radar transceiver with embedded control logic is implemented using a 130-nm complementary metal oxide semiconductor. Clock signals drive the radar operation. Signal-to-noise ratio enhancements are achieved using the repetitive coherent clock schemes. The hand-held prototype radar that uses the TTWR SoC operates in real time, allowing seamless data capture, processing, and display of the target information. The prototype is tested under various pseudo-disaster conditions. The test standards and methods, developed along with the system, are also presented.

• Journal of Institute of Control, Robotics and Systems
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• v.22 no.8
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• pp.671-677
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• 2016

A Controller Area Network (CAN) is a serial communication protocol that is highly reliable and efficient in many aspects, such as wiring cost and space, system flexibility, and network maintenance. Therefore, it is chosen for the communication protocol between a single chip controller based on Field Programmable Gate Array (FPGA) and peripheral devices. In this paper, the design and implementation of CAN IP, which is written in VHSIC Hardware Description Language (VHDL), is presented. The implemented CAN IP is based on the CAN 2.0A specification. The CAN IP consists of three processes: clock generator, bit timing, and bit streaming. The clock generator process generates a time quantum clock. The bit timing process does synchronization, receives bits from the Rx port, and transmits bits to the Tx port. The bit streaming process generates a bit stream, which is made from a message received from a micro controller subsystem, receives a bit stream from the bit timing process, and handles errors depending on the state of the CAN node and CAN message fields. The implemented CAN IP is synthesized and downloaded into SmartFusion FPGA. Simulations using ModelSim and chip test results show that the implemented CAN IP conforms to the CAN 2.0A specification.

• BMB Reports
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• v.50 no.5
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• pp.235-236
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• 2017

The circadian clock is an internal system that is synchronized by external stimuli, such as light and temperature, and influences various physiological and developmental processes in living organisms. In the model plant Arabidopsis, transcriptional, translational and post-translational processes are interlocked by feedback loops among morning- and evening-phased genes. In a post-translational loop, plant-specific single-gene encoded GIGANTEA (GI) stabilize the F-box protein ZEITLUPE (ZTL), driving the targeted-proteasomal degradation of TIMING OF CAB EXPRESSION 1 (TOC1) and PSEUDO-RESPONSE REGULATOR 5 (PRR5). Inherent to this, we demonstrate the novel biochemical function of GI as a chaperone and/or co-chaperone of Heat-Shock Protein 90 (HSP90). GI prevents ZTL degradation as a chaperone and facilitates ZTL maturation together with HSP90/HSP70, enhancing ZTL activity in vitro and in planta. GI is known to be involved in a wide range of physiology and development as well as abiotic stress responses in plants, but it could also interact with diverse client proteins to increase protein maturation. Our results provide evidence that GI helps proteostasis of ZTL by acting as a chaperone and a co-chaperone of HSP90 for proper functioning of the Arabidopsis circadian clock.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.10
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• pp.1804-1809
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• 2006

The aim of this Paper is to describe the implementation of a low-power digital front-End Design (FED) that will act as the core of a stand-alone Power dissipation methodology. The design of digital integrated circuits is a large and diverse area, and we have chosen to focus on low power FED. Designs are made from synthesized logic, and we need to consider the low power digital FED including input clock, buffer, latches, voltage regulator, and capacitance-to-voltage counter which have been integrated onto hish bandwidth communication chips and system. These single- chip micro instruments, implemented in a 0.12um CMOS technology operate with a single 0.9V supply voltage, and can be used to monitor dynamic and static power dissipation, Vesture, acceleration junction temperature (Tj), etc.