• 한국세라믹학회지
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• 제32권3호
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• pp.371-377
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• 1995

Silicon oxide films were grown on single-crystal silicon substrates at low temperatures (25~205$^{\circ}C$) in a low pressure electron cyclotron resonance (ECR) oxygen plasma. The growth rate of the silicon oxide film increased as the temperature increased or the pressure decreased. Also, the thickness of the silicon oxide film increased at negative bias voltage, but not changed at positive bias voltage. The growth law of the silicon oxide film was approximated to the parabolic form. Capacitance-voltage (C-V) and current density-electric field (J-E) characteristics were studied using Al/SiO2/p-Si MOS structures. For a 10.2 nm thick silicon oxide film, the leakage current density at the electric field of 1 MVcm-1 was less than 1.0$\times$10-8Acm-2 and the breakdown field was higher than 10 MVcm-1. The flat band voltage of Al/SiO2/p-Si MOS capacitor was varied in the range of -2~-3 V and the effective dielectric constant was 3.85. These results indicate that high quality oxide films with properties that are similar to those of thermal oxide film can be fastly grown at low temperature using the ECR oxygen plasma.

• Transactions on Electrical and Electronic Materials
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• 제14권5호
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• pp.250-253
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• 2013

In this paper, we fabricated 3D pillar type silicon-oxide-nitride-oxide-silicon (SONOS) devices for high density flash applications. To solve the limitation between erase speed and data retention of the conventional SONOS devices, bandgap-engineered (BE) tunneling oxide of oxide-nitride-oxide configuration is integrated with the 3D structure. In addition, the tunneling oxide is modulated by another method of $N_2$ ion implantation ($N_2$ I/I). The measured data shows that the BE-SONOS device has better electrical characteristics, such as a lower threshold voltage ($V_{\tau}$) of 0.13 V, and a higher $g_{m.max}$ of 18.6 ${\mu}A/V$ and mobility of 27.02 $cm^2/Vs$ than the conventional and $N_2$ I/I SONOS devices. Memory characteristics show that the modulated tunneling oxide devices have fast erase speed. Among the devices, the BE-SONOS device has faster program/erase (P/E) speed, and more stable endurance characteristics, than conventional and $N_2$ I/I devices. From the flicker noise analysis, however, the BE-SONOS device seems to have more interface traps between the tunneling oxide and silicon substrate, which should be considered in designing the process conditions. Finally, 3D structures, such as the pillar type BE-SONOS device, are more suitable for next generation memory devices than other modulated tunneling oxide devices.

• 전기학회논문지
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• 제65권10호
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• pp.1702-1705
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• 2016

We propose a novel hydrogen-reduced p-type amorphous silicon oxide buffer layer between $TiO_2$ antireflection layer and p-type silicon window layer of silicon thin film solar cells. This new buffer layer can protect underlying the $TiO_2$ by suppressing hydrogen plasma, which could be made by excluding $H_2$ gas introduction during plasma deposition. Amorphous silicon oxide thin film solar cells with employing the new buffer layer exhibited better conversion efficiency (8.10 %) compared with the standard cell (7.88 %) without the buffer layer. This new buffer layer can be processed in the same p-chamber with in-situ mode before depositing main p-type amorphous silicon oxide window layer. Comparing with state-of-the-art buffer layer of AZO/p-nc-SiOx:H, our new buffer layer can be processed with cost-effective, much simple process based on similar device performances.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제43회 하계 정기 학술대회 초록집
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• pp.253-253
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• 2012

Low temperature SiOx film process has being required for both silicon and oxide (IGZO) based low temperature thin film transistor (TFT) for application of flexible display. In recent decades, from low density and high pressure such as capacitively coupled plasma (CCP) type plasma enhanced chemical vapor deposition (PECVD) to the high density plasma and low pressure such as inductively coupled plasma (ICP) and electron cyclotron resonance (ECR) have been used to researching to obtain high quality silicon oxide (SiOx) thin film at low temperature. However, these plasma deposition devices have limitation of controllability of process condition because process parameters of plasma deposition such as RF power, working pressure and gas ratio influence each other on plasma conditions which non-leanly influence depositing thin film. In compared to these plasma deposition devices, neutral beam assisted chemical vapor deposition (NBaCVD) has advantage of independence of control parameters. The energy of neutral beam (NB) can be controlled independently of other process conditions. In this manner, we obtained NB dependent high crystallized intrinsic and doped silicon thin film at low temperature in our another papers. We examine the properties of the low temperature processed silicon oxide thin films which are fabricated by the NBaCVD. NBaCVD deposition system consists of the internal inductively coupled plasma (ICP) antenna and the reflector. Internal ICP antenna generates high density plasma and reflector generates NB by auger recombination of ions at the surface of metal reflector. During deposition of silicon oxide thin film by using the NBaCVD process with a tungsten reflector, the energetic Neutral Beam (NB) that controlled by the reflector bias believed to help surface reaction. Electrical and structural properties of the silicon oxide are changed by the reflector bias, effectively. We measured the breakdown field and structure property of the Si oxide thin film by analysis of I-V, C-V and FTIR measurement.

• Transactions on Electrical and Electronic Materials
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• 제4권6호
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• pp.32-37
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• 2003

In this paper, the trap characteristics of thin silicon oxides is investigated in the ULSI implementation with nano structure transistors. The stress and transient currents associated with the on and off time of applied voltage were used to measure the distribution of high voltage stress induced traps in thin silicon oxide films. The stress and transient currents were due to the charging and discharging of traps generated by high stress voltage in the silicon oxides. The transient current was caused by the tunnel charging and discharging of the stress generated traps nearby two interfaces. The stress induced leakage current will affect data retention in electrically erasable programmable read only memories. The oxide current for the thickness dependence of stress current, transient current, and stress induced leakage currents has been measured in oxides with thicknesses between 113.4nm and 814nm, which have the gate area 10$\^$-3/ $\textrm{cm}^2$. The stress induced leakage currents will affect data retention, and the stress current and transient current is used to estimate to fundamental limitations on oxide thicknesses.

• The Korean Journal of Ceramics
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• 제3권1호
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• pp.34-36
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• 1997

We have fabricated a patterned diamond field emitter on a silicon substrate. Fine diamond particles were planted on a silicon wafer using conventional scratch method. A silicon oxide film was deposited on the substrate seeded with diamond powder. An array of holes was patterned on the silicon oxide film using VLSI processing technology. Diamond grains were grown using a microwave plasma-assisted chemical vapor deposition. Because diamond could not grow on the silicon oxide barrier, diamond grains filled only the patterned holes in the silicon oxide film, resulting in an array of diamond tips.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 춘계학술대회 논문집 전자세라믹스 센서 및 박막재료 반도체재료 일렉트렛트 및 응용기술
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• pp.43-46
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• 2000

In this paper, the stress and transient currents associated with the on and off time of applied voltage were used to measure the density and distribution of high voltage stress induced traps in thin silicon oxide films. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface. The trap densities were dependent on the stress polarity. The stress generated trap distributions were relatively uniform the order of $10^{11}\sim10^{21}$[states/eV/$cm^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}\sim10^{13}$[states/eV/$cm^2$]. It appear that the stress and transient current that flowed when the stress voltage were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 춘계학술발표강연 및 논문개요집
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• pp.107-107
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• 2003

원자층 증착(ALD, Atomic Layer Deposition)기술은 기판 표면에서의 self-limiting reaction을 통해 매우 얇은 박막을 형성할 수 있고, 두께 및 조성 제어를 정확히 할 수 있으며, 복잡한 형상의 기판에서도 100%에 가까운 step coverage를 얻을 수 있어 초미세패턴의 형성과 매우 얇은 두께에서 균일한 물리적, 전기적 특성이 요구되는 초미세 반도체 공정에 적합하다. 특히 반도체의 logic 및 memory 소자의 gate 공정에서 절연막과 보호막으로, 그리고 배선공정에서는 층간절연막(ILD, Inter Layer Dielectric)으로 사용하는 silicon oxide 박막에 적용될 경우, LPCVD 방법에 비해 낮은 온도에서 증착이 가능해 boron과 같은 dopant들의 확산을 최소화하여 transistor 특성 향상이 가능하며, PECVD 방법에 비해 전기적·물리적 특성이 월등히 우수하고 대면적 uniformity 증가가 기대된다. 본 연구에서는 자체적으로 설계 및 제작한 장비를 이용하여 silicon oxide 박막을 ALD 방법으로 증착하고 그 특성을 살펴보았다. 먼저, cycle 수에 따른 증착 박막 두께의 linearity를 통해서 원자층 증착(ALD)임을 확인할 수 있었으며, reactant exposure(L)와 증착 온도에 따른 deposition rate 변화를 알아보았다 Elipsometer를 이용해 증착된 silicon oxide 박막의 두께 및 굴절률과 그 uniformity를 관찰하였고, AES 및 XPS 분석 장비로 박막의 조성비와 불순물 성분을 살펴보았으며, 증착 박막의 치밀성 평가를 위해 HF etchant로 wet etch rate를 측정하여 물리적 특성을 정리하였다. 특히, 기존의 박막 증착 방법인 LPCVD와 PECVD에 의한 silicon oxide박막의 물성과 비교, 평가해 보았다. 나아가 적절한 촉매 물질을 선정하여 원자층 증착(ALD) 공정에 적용하여 그 효과도 살펴보았다.

• 전자공학회논문지D
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• 제34D권1호
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• pp.35-40
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• 1997

A new method to form the gate oxide and recrystllize the polycrystalline silicon (poly-Si) active layer simultaneously is proposed and fabricated successfully. During te irradiation of excimer laser, the poly-Si film is recrystallized, while the oxygen ion impurities injected into the amorphous silicon(a-Si) film are activated by laser energy and react with silicon atoms to form SiO2. We investigated the characteristics of the sample fabricated by proposed method using AES, TEM, AFM. The electrical performance of oxide was verified by ramp up voltage method. Our experimental results show that a high quality oxide, a pol-Si film with fine grain, and a smooth and clean interface between oxide and poly-Si film have been successfully obtained by the proposed fabrication method. The interface roughness of oxide/poly-Si fabricated by new method is superior to film by conventional fabrication os that the proposed method may improve the performance of poly-Si TFTs.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.727-730
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• 2003

Thin tin oxide film with nano-size particle was prepared on silicon substrate by hydrothermal synthetic method and successive sol-gel spin coating method. The fabrication method of tin oxide film with ultrafine nano-size crystalline structure was tried to be applied to fabrication of micro gas sensor array on silicon substrate. The tin oxide film on silicon substrate was well patterned by chemical etching upto 5${\mu}{\textrm}{m}$width and showed very uniform flatness. The tin oxide film preparation method and patterning method were successfully applied to newly proposed 2-dimensional micro sensor fabrication.