• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.167-170
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• 2002

The influence of Si surface damage on Ni-silicide with TiN Capping layer and the effect of $H_2$ anneal are characterized. Si surface is intentionally damaged using Ar Sputtering. The sheet resistance of NiSi formed on damaged silicon increased rapidly as Ar sputtering time increased. However, the thermal stability of Ni-Si on the damage silicon was more stable than that on at undamaged Si, which means that damaged region retards the formation of NiSi. It was shown that $H_2$ anneal and TiN capping is highly effective in reducing NiSi sheet resistance.

• Korean Journal of Materials Research
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• v.11 no.9
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• pp.776-780
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• 2001

$SiO_2$ and polycrystalline Si layers were sequentially grown on (100) Si. NiSi was formed on this substrate from a 20nm Ni layer or a 20nm Ni/5nm Ti bilayer by rapid thermal annealing (RTA) at $300~500^{\circ}C$ to compare thermal stability. In addition, MOS capacitors were fabricated by depositing a 20nm Ni layer on the Poly-Si/$SiO_2$substrate, RTA at $400^{\circ}C$ to form NiSi, $BF_2$ or As implantation and finally drive- in annealing at $500~800^{\circ}C$ to evaluate electrical characteristics. When annealed at $400^{\circ}C$, NiSi made from both a Ni monolayer and a Ni/Ti bilayer showed excellent thermal stability. But NiSi made from a Ni/Ti bilayer was thermally unstable at $500^{\circ}C$. This was attributed to the formation of insignificantly small amount of NiSi due to suppressed Ni diffusion through the Ti layer. PMOS and NMOS capacitors made by using a Ni monolayer and the SADS(silicide as a dopant source) method showed good C-V characteristics, when drive-in annealed at $500^{\circ}C$ for 20sec., and$ 600^{\circ}C$ for 80sec. respectively.

• Journal of Powder Materials
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• v.6 no.1
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• pp.103-110
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• 1999

Different sizes of Si powder and milling medium materials (steel and partially stabilized zirconia (PSZ)) were used to synthesize $Ti_3Si$ and $TiSi_2$ by mechanical aollying (MA) of Ti-25.0.at.%Si and Ti-66.7at.% Si powder mixtures. the formation of each titanium silicide did not occur even after 360 min of MA of as-re-ceived Si and Ti powder mixtures due to the lack of homogeneity. $Ti_3Si$, however, was synthesized after 240 min of MA of Ti and 60 min-premilled Si powder mixture. ${\alpha}-TiSi_2$ and $TiSi_2$ were produced by jar milling of Ti and 60 min-premilled Si powder mixture for 48 hr and high -energy PSZ ball-milling in a steel vial for 360 min. The formation of each titanium silicide was characterized by a slow reaction rate as the reactants and product(s) coexisted for a certain period of time. The formation of $Ti_3Si$ and $TiSi_2$ and the reaction rates appeared to be influenced by the Si particle size, the homogeneity of the powder mixtures and the milling medium materials.

• Journal of the Korean Vacuum Society
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• v.10 no.1
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• pp.72-80
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• 2001

In this paper, we present a systematic method of extracting the input parameters of poly-Si TFT(Thin-Film Transistor) for Spice simulations. This method has been applied to two different types of poly-Si TFTs such as ELA (Excimer Laser Annealing) and SMC (Silicide Mediated Crystallization) with good fitting results to experimental data. Among the Spice circuit simulators, the PSpice has the GUI(graphic user interface) feature making the composition of complicated circuits easier. We added successfully the poly-Si TFT model of AIM-Spice to the PSpice simulator, and analyzed easily to compare the electrical characteristics of pixels without or with the line RC delay. In the comparative results, the ELA poly-Si TFT is superior to the SMC poly-Si TFT in the charging time and the kickback voltage for the TFT-LCD (Thin Film Transistor-Liquid Crystal Display).

• Proceedings of the Materials Research Society of Korea Conference
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• 1993.05a
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• pp.64-65
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• 1993

MPB 조성영역인 Zr/Ti=52/48의 composite ceramic target을 사용하여 RF magnetron sputtering 방법으로 기판온도 약 30$0^{\circ}C$에서 RZT 박막을 Pt/Ti/Si 기판위에 증착시켰다. 안정상인 perovskite 구조를 형성시키기 위하여 PbO분위기에서 furnace annealing 과 Repid thermal annealing을 실시하여 열처리 방법에 따른 상형성 및 계면반응과 그에 따른 전기적 특성을 고찰 하였다. Pt 의 두께가 250$\AA$인 경우 furnace annealing 시 $650^{\circ}C$에서 perouskite 상이 형성되었으나 Pt층이 산소의 확산을 방지하지 못하여 상부의 Ti 층이 TiOx로 변태하였으며 하부의 Ti는 Si 과 반응하여 Ti-silicide 롤 변태하였다. 또한 75$0^{\circ}C$,60sec 인 경우 Pt 층의 응집화가 관찰되어 하부전극으로서 적용이 적절하지 못하다. 급속열처리를 실시한 경우에도 마찬가지로 Ti 층이 TiOx 와 silicide 층으로 변태되었다. Pt의 두께가 1000$\AA$인 경우에도 250$\AA$와는 달리 RTA 시 (III)방향으로 Furace annealing 시(001)방향으로 우선 성장하였다. 이는 Ti(001), P(111),PZT(111)면의 lattic mismatch 가 매우 작은데다 RTA 시 계면반응이 거의발생하지 않아 PZT 박막이 (111) 방향으로 우선 성장한 것으로 보인다. Furnace annealing 경우는 심한 계면반응이 발생하여 Pt층에 어느 정도 영향을 주었기 때문에 우선성장 방향이 바뀌었다구 생각한다.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 1998.05a
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• pp.405-408
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• 1998

In this paper, We analyzed the current-voltage characteristics with n-type silicon substrates concentration and temperature variations (Room temperature, 5$0^{\circ}C$, 75$^{\circ}C$) in platinum silicide and silicon junction. Measurement electrical parameters are forward turn-on voltage, reverse breakdown voltage, barrier height, saturation current, ideality factor, dynamic resistance acceding to junction concentration of substrates and temperature variations. As a result, the forward turn-on voltage, reverse breakdown voltage, barrier height and dynamic resistance were decreased but saturation current and ideality factor were increased by substrates concentration variations. Reverse breakdown voltage and dynamic resistance were increased by temperature variations.

• Journal of the Korean Vacuum Society
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• v.9 no.3
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• pp.267-272
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• 2000

Electroplating Cu was deposited on Si(100) wafer after seed Cu was deposited by sputtering first. TaN was deposited as a diffusion barrier before depositing the seed Cu. Electroplating Cu thin films show highly (111)-oriented microstructure for both before and after annealing at $450^{\circ}C$ for 30min and no copper silicide was detected in the same samples, which indicates that TaN barrier layer blocks well the Cu diffusion into silicon substrate. After annealing the electroplating Cu film up to $450^{\circ}C$, the Cu film became columnar from non-columnar, its grain size became larger about two times, and also defects density of stacking faults, twins and dislocations decreased greatly. Thus the heat treatment will improve significantly electromigration property caused by the grain boundary in the Cu thin films.

• Korean Journal of Materials Research
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• v.6 no.8
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• pp.808-816
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• 1996

(100) Si 기판위에 전자 빔 증착법을 이용하여$ 90\AA$두께의 Ti과 $120\AA$두께의 Co를 순차적으로 증착시켰다. 그 후 질소분위기하의 $350-900^{\circ}C$온도구간에서 급속열처리함으로써 (100) Si 기판위의 Co/Ti 이중 박막의 실리사이드화 반응이 일어나게 했으며 이를 XRD, AES, TEM을 이용하여 분석하였다. $500^{\circ}C$이하의 온도에서는 Co원자들이 Ti층쪽으로 빠르게 확산하여 Si와 반응하기 이전에 Ti원자들과 상호 혼합되어 어떠한 실리사이드도 형성되지 않았다. $500^{\circ}C$에서 열처리된 시편의 고분해능전자현미경 영상을 통해 Co-Ti 혼합층과 실리콘 기판과의 계면에서 (100)Si 기판과 정합관계를 가지는 CoSi2가 형성되었음을 확인했다. $600^{\circ}C$열처리에 의해 Co-Ti-Sitka성분 실리사이드가 형성되기 시작하였으며, 형성된 삼성분 실리사이드는 Ti의 out-diffusion에 의해 $900^{\circ}C$ 이상의 온도에서는 불안정하였다. Co/Ti이중 박막에 의해 형성된 CoSi2는 실리콘 기판과 평탄한 계면을 가지며 실리콘 기판에 대해 (100)우선성장방위를 가졌다.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.19 no.4
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• pp.159-164
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• 2009

We fabricated 40 nm-thick cobalt silicide ($CoSi_2$) as a buffer layer, on p-type Si(100) and Si(111) substrates to investigate the possibility of GaN epitaxial growth on $CoSi_2$/Si substrates. We deposited GaN using a HVPE (hydride vapor phase epitaxy) with two processes of process I ($850^{\circ}C$-12 minutes + $1080^{\circ}C$-30 minutes) and process II ($557^{\circ}C$-5 minutes + $900^{\circ}C$-5 minutes) on $CoSi_2$/Si substrates. An optical microscopy, FE-SEM, AFM, and HR-XRD (high resolution X-ray diffractometer) were employed to determine the GaN epitaxy. In case of process I, it showed no GaN epitaxial growth. However, in process II, it showed that GaN epitaxial growth occurred. Especially, in process II, GaN layer showed selfaligned substrate separation from silicon substrate. Through XRD ${\omega}$-scan of GaN <0002> direction, we confirmed that the combination of cobalt silicide and Si(100) as a buffer and HVPE at low temperature (process II) was helpful for GaN epitaxy growth.

• Journal of the Korean Vacuum Society
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• v.6 no.2
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• pp.143-150
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• 1997

In this study, doffusion barrier properties of 1000 $\AA$ thick molybdenum compound(Mo, Mo-N, $MoSi_2$, Mo-Si-N) films were investigated using sheet resistance measurement, X-ray diffraction(XRD), X-ray photoelectron spectroscopy(XPS), Scanning electron mircoscopy(SEM), and Rutherford back-scattering spectrometry(RBS). Each barrier material was deposited by the dc magnetron sputtering and annealed at 300-$800^{\circ}C$ for 30 min in vacuum. Mo and MoSi2 barrier were faied at low temperatures due to Cu diffusion through grain boundaries and defects in Mo thin film and the reaction of Cu with Si within $MoSi_2$, respectively. A failure temperature could be raised to $650^{\circ}C$-30 min in the Mo barrier system and to $700^{\circ}C$-30 min in the Mo-silicide system by replacing Mo and $MoSi_2$ with Mo-N and Mo-Si-N, respectively. The crystallization temperature in the Mo-silicide film was raised by the addition of $N_2$. It is considered that not only the $N_2$, stuffing effect but also the variation of crystallization temperature affects the reaction of Cu with Si within Mo-silicide. It is found that Mo-Si-N is the more effective barrier than Mo, $MoSi_2$, or Mo-N to copper penetraion preventing Cu reaction with the substrate for $30^{\circ}C$min at a temperature higher than $650^{\circ}C$.