• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.8 no.4
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• pp.263-269
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• 2015

Digital watermarking is imperceptible and statistically undetectable information embeds into digital data. Most information in digital audio watermarking schemes have used binary random sequences. The embedded binary random sequence distorts and modifies the original data while it plays a vital role in security. In this paper, a binary random sequence to improve imperceptibility in perceptual region of the human auditory system is proposed. The basic idea of this work is a modification of a binary random sequence according to the frequency analysis of adjacent binary digits that have different signs in the sequence. The canonical signed digit code (CSDC) is also applied to modify a general binary random sequence and the pair-matching function between original and its modified version. In our experiment, frequency characteristics of the proposed binary random sequence was evaluated and analyzed by Bark scale representation of frequency and frequency gains.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.6C
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• pp.632-639
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• 2002

To reduce the area and power consumption in constant coefficient multiplications, the constant coefficient can be encoded using canonic signed digit(CSD) representation. When the partial product terms are added depending on the nonzero bit(1 or -1) positions in the CSD-encoded multiplier, all sign bits are properly extended before the addition takes place. In this paper, to reduce the overhead due to sign extension, a new method is proposed based on the fact that carry propagation in the sign extension part can be controlled such that a desired input bit can be propagated as a carry. Also, a fixed-width multiplier design method suitable for CSD multiplication is proposed. As an application, 43-tap filbert transformer for SSB/BPSK-DS/CDMA is implemented. It is shown that, about 16∼28% adders can be saved by the proposed method compared with the conventional methods.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.34-45
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• 2007

Digital decimation filter is inevitable in oversampled sigma-delta A/D converters for the sake of reducing the oversampled rate to Nyquist rate. This paper presented a Verilog-HDL design and implementation of an area-efficient digital decimation filter that provides time-to-market advantage for sigma-delta analog-to-digital converters. The digital decimation filter consists of CIC(cascaded integrator-comb) filter and two cascaded half-band FIR filters. A CSD(canonical signed digit) representation of filter coefficients is used to minimize area and reduce in hardware complexity of multiplication arithmetic. Coefficient multiplications are implemented by using shifters and adders. This three-stage decimation filter is fabricated in $0.25-{\mu}m$ CMOS technology and incorporates $1.36mm^2$ of active area, shows 4.4 mW power consumption at clock rate of 2.8224 MHz. Measured results show that this digital decimation filter is suitable for digital audio decimation filters.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.4
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• pp.637-637
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• 1997

In this paper, format conversion filters are proposed, which have advantages in hardware implementation compared to the ones proposed in MPEG-4 Video Verification Model. since each coefficients of the proposed filters is constrained to have less than two non-zero digits in minimal signed digit representation, multiplication of input and the coefficient can be implemented by a single adder. As a result, the proposed filters have advantages in hardware complexity and speed, compared to the filters which are usually implemented by integer multiplier or carry save adders. Six kinds of filters are proposed in MPEG-4 Video Verification Model for size conversion of 2:1, 4:1, 5:3 and 5:6. We design 5 filters for the same purpose and compare the performance. The remaining one is very simple to implement. For comparing the filtering performance, we first compare the results of sine wave frequency conversion as an indirect but meaningful comparison. Second. We compute the PSNR of the images obtained from the proposed filters and the ones proposed by MPEG, with reference to the images obtained by using double precision arithmetic and high order filter. The results show that the performance of the proposed filters is almost the same as that of the filters proposed by MPEG. In conclusion, the peroformance of the proposed filters is comparable to that of the ones in MPEG-4, while requiring lower hardware complexity and providing high operating speed.

• Journal of the Korea Institute of Information Security & Cryptology
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• v.17 no.1
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• pp.21-32
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• 2007

Vuillaume-Okeya presented unsigned receding methods for protecting modular exponentiations against side channel attacks, which are suitable for tamper-resistant implementations of RSA or DSA which does not benefit from cheap inversions. The proposed method was using a signed representation with digits set ${1,2,{\cdots},2^{\omega}-1}$, where 0 is absent. This receding method was designed to be computed only from the right-to-left, i.e., it is necessary to finish the receding and to store the receded string before starting the left-to-right evaluation stage. This paper describes new receding methods for producing SPA-resistant unsigned representations which are scanned from left to right contrary to the previous ones. Our contributions are as follows; (1) SPA-resistant unsigned left-to-right receding with general width-${\omega}$, (2) special case when ${\omega}=1$, i.e., unsigned binary representation using the digit set {1,2}, (3) SPA-resistant unsigned left-to-right Comb receding, (4) extension to unsigned radix-${\gamma}$ left-to-right receding secure against SPA. Hence, these left-to-right methods are suitable for implementing on memory limited devices such as smartcards and sensor nodes