• Title/Summary/Keyword: shifters

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The Design of Electronically Beam Steeling Array Antenna Using 4 Parasitic Elements (4개의 기생 소자를 이용한 전자적인 빔 조향 배열 안테나 설계)

  • Kim, Young-Goo;Choi, Ik-Guen;Kim, Tae-Hong;You, Jong-Jun;Kang, Sang-Gee
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.20 no.2
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    • pp.167-173
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    • 2009
  • This paper proposes an electronically beam steering array antenna, consisting of single fed active element and 4 parasitic elements, operating in 5.8 GHz ISM band. Beam steering can be achieved by controlling the reactance of the variable reactance control circuit connected to the load of the parasitic elements without using the high cost phase shifters. The proposed antenna realizes ${\pm}30^{\circ}$ beam scanning of E-plane and H-plane with the below -10 dB return loss in ISM band. The gain of the $6.18{\sim}7.53\;dBi$ in E-plane and $7.022{\sim}7.779\;dBi$ in H-plane is shown in the scanning range.

Design of Low Cost H.264/AVC Entropy Coding Unit Using Code Table Pattern Analysis (코드 테이블 패턴 분석을 통한 저비용 H.264/AVC 엔트로피 코딩 유닛 설계)

  • Song, Sehyun;Kim, Kichul
    • Journal of IKEEE
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    • v.17 no.3
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    • pp.352-359
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    • 2013
  • This paper proposes an entropy coding unit for H.264/AVC baseline profile. Entropy coding requires code tables for macroblock encoding. There are patterns in codewords of each code tables. In this paper, the patterns between codewords are analyzed to reduce the hardware cost. The entropy coding unit consists of Exp-Golomb unit and CAVLC unit. The Exp-Golomb unit can process five code types in a single unit. It can perform Exp-Golomb processing using only two adders. While typical CAVLC units use various code tables which require large amounts of resources, the sizes of the tables are reduced to about 40% or less of typical CAVLC units using relationships between table elements in the proposed CAVLC unit. After the Exp-Golomb unit and the CAVLC unit generate code values, the entropy unit uses a small size shifter for bit-stream generation while typical methods are barrel shifters.

Variable Radix-Two Multibit Coding and Its VLSI Implementation of DCT/IDCT (가변길이 다중비트 코딩을 이용한 DCT/IDCT의 설계)

  • 김대원;최준림
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.39 no.12
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    • pp.1062-1070
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    • 2002
  • In this paper, variable radix-two multibit coding algorithm is presented and applied in the implementation of discrete cosine transform(DCT) and inverse discrete cosine transform(IDCT). Variable radix-two multibit coding means the 2k SD (signed digit) representation of overlapped multibit scanning with variable shift method. SD represented by 2k generates partial products, which can be easily implemented with shifters and adders. This algorithm is most powerful for the hardware implementation of DCT/IDCT with constant coefficient matrix multiplication. This paper introduces the suggested algorithm, it's proof and the implementation of DCT/IDCT The implemented IDCT chip with 8 PEs(Processing Elements) and one transpose memory runs at a tate of 400 Mpixels/sec at 54MHz frequency for high speed parallel signal processing, and it's verified in HDTV and MPEG decoder.

A Hadamard Matrix Feed Network for a Dual-Beam Forming Array Antenna (두 개의 빔 형성 안테나를 위한 Hadamard 행렬 급전 장치)

  • Kim, Jae-Hee;Jo, Gyu-Young;Park, Wee-Sang
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.19 no.8
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    • pp.927-932
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    • 2008
  • We propose a novel $4{\times}4$ Hadamard matrix feed network for a $4{\times}1$ array antenna to form a dual beam. If each element of the array is excited following the elements in a row of the Hadamard matrix, a two-lobed antenna beam can be obtained. The angle between the two lobes can be controlled. The Hadamard matrix feed network consists of four $90^{\circ}$ hybrids, a crossover and four $90^{\circ}$ phase shifters. The array, including the Hadamard matrix feed network, was fabricated on a microstip structure. The measured beam directions of the two lobes are $0^{\circ}$, ${\pm}15^{\circ}$, ${\pm}33^{\circ}$, ${\pm}45^{\circ}$ depending on the choice of the input port of the feed network.

Broadband 90° Schiffman Phase Shifter Using Slot-Coupled Lines (슬롯-결합 선로를 이용한 광대역 90° 쉬프만 위상천이기)

  • Rhee, Seung-Yeop
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.23 no.10
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    • pp.1145-1150
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    • 2012
  • In this paper, an improved Schiffman phase shifter is proposed using slot-coupled lines. It consists of the typical coupled lines and a simple rectangular slot which is placed in the ground plane underneath the coupled lines. Phase responses of the slot-coupled Schiffman phase shifter are analyzed in consideration of the phase velocity of two independent transmission modes and the characteristic impedance of slot-coupled line. The $905^{\circ}$ Schiffman phase shifters with high impedance ratio is realized at 2.4 GHz, which cannot be implemented with the conventional coupled lines. The measured results show that the bandwidth is around 74.2 % within the phase errors ${\pm}5^{\circ}$. The measured return loss is found to be better than 15.0 dB and insertion loss is less than 1.5 dB over the operating frequency band.

Broadband 90° Schiffman Phase Shifter with Vertically Installed Coupled Lines (수직 장착된 결합선로를 이용한 광대역 90° 쉬프만 위상천이기)

  • Rhee, Seung-Yeop
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.25 no.7
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    • pp.721-727
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    • 2014
  • In this paper, an broadband Schiffman phase shifter is proposed using vertically installed coupled lines. It consists of the typical coupled lines and a extra coupled lines which is installed vertically on the original coupled lines plane. Phase responses of Schiffman phase shifter with vetically installed coupled lines are analyzed in consideration of the phase velocity of two independent transmission modes and the characteristic impedances. The $90^{\circ}$ Schiffman phase shifters with high impedance ratio is realized at 2.4 GHz, which cannot be implemented with the conventional coupled lines. The measured results show that the bandwidth is 1.5~3.2 GHz(70.8 %) within the phase errors ${\pm}5^{\circ}$. The measured return loss is found to be better than 12.4 dB and insertion loss is less than 1.2 dB over the operating frequency band.

The Efficient 32×32 Inverse Transform Design for High Performance HEVC Decoder (고성능 HEVC 복호기를 위한 효율적인 32×32 역변환기 설계)

  • Han, Geumhee;Ryoo, Kwangki
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.4
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    • pp.953-958
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    • 2013
  • In this paper, an efficient hardware architecture is proposed for $32{\times}32$ inverse transform HEVC decoder. HEVC is a new image compression standard to deal with much larger image sizes compared with conventional image codecs, such as 4k, 8k images. To process huge image data effectively, it adopts various new block structures. Theses blocks consists of $4{\times}4$, $8{\times}8$, $16{\times}16$, and $32{\times}32$ block. This paper suggests an effective structures to process $32{\times}32$ inverse transform. This structure of inverse transform adopts the decomposed $16{\times}16$ matrixes of $32{\times}32$ matrix, and simplified the operations by implementing multiplying with shifters and adders. Additionally the operations frequency is downed by using multicycle paths. Also this structure can be easily adopted to a multi-size transform or a forward transform block in HEVC codec.

Analog Ferrite Phase Shifter Using Substrate Integrated Waveguide (기판 집적 도파관을 이용한 아날로그 페라이트 위상 천이기)

  • Yim, Myung-Gyu;Byun, Jin-Do;Lee, Hai-Young
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.22 no.4
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    • pp.470-480
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    • 2011
  • Analog ferrite phase shifters based on rectangular waveguides which are used as component of passive phased array system have high power handling capability, but it is heavy and has high cost to fabricate. In this paper, we propose an analog ferrite phase shifter using substrate integrated waveguide(SIW), which has low cost and is easy to fabricate because it uses printed circuit board(PCB) process. The proposed structure is fabricated by using centeral dielectric material removal for inserting a ferrite bar. The measured results show that the proposed structure has not only $5.1^{\circ}$/mm phase variation but also return loss variation under 12.9 dB. Therefore, it is expected that the proposed phase shifter can plays an role to reduce weight and to has low cost on the phased array system.

Compressed Sensing Techniques for Millimeter Wave Channel Estimation (밀리미터파 채널 추정을 위한 압축 센싱 기법)

  • Han, Yonghee;Lee, Jungwoo
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.42 no.1
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    • pp.25-30
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    • 2017
  • Millimeter wave (mmWave) bands are expected to improve date rate of 5G systems due to the wide available bandwidth. While severe path loss in those bands has impeded the utilization, short wavelength enables a large number of antennas packed in a compact form, which can mitigate the path loss. However, estimating the channel with a conventional scheme requires a huge training overhead, hence an efficient estimation scheme operating with a small overhead needs to be developed. The sparsity of mmWave channels caused by the limited scatterers can be exploited to reduce the overhead by utilizing compressed sensing. In this paper, we introduce compressed sensing techniques for mmWave channel estimation. First, we formulate wideband channel estimation into a sparse recovery problem. We also analyze the characteristics of random measurement matrix constructed using quantized phase shifters in terms of mutual incoherence.

CORDIC using Heterogeneous Adders for Better Delay, Area and Power Trade-offs (향상된 연산시간, 회로면적, 소비전력의 절충관계를 위한 혼합가산기 기반 CORDIC)

  • Lee, Byeong-Seok;Lee, Jeong-Gun;Lee, Jeong-A
    • Journal of the Korea Society of Computer and Information
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    • v.15 no.2
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    • pp.9-18
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    • 2010
  • High performance is required with small size and low power in the mobile embedded system. A CORDIC algorithm can compute transcendental functions effectively with only small adders and shifters and is suitable one for the mobile embedded system. However CORDIC unit has performance degradation according due to iterative inter-rotations. Adder design is an important design unit to be optimized for a high performance and low power CORDIC unit. It is necessary to explore the design space of a CORDIC unit considering trade-offs of an adder unit while satisfying delay, area and power constraints. In this paper, we suggest a CORDIC architecture employing a heterogeneous adder and an optimization methodology for producing better optimal tradeoff points of CORDIC designs.