• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.33B no.5
• /
• pp.41-51
• /
• 1996

In this paper, anew parallel processing system based on a cluster architecture which provides scalability of a parallel processing system while maintains shared memory multiprocessor characteristics is proposed. In recent days low cost, high performnce microprocessors have led to construction of large scale parallel processing systems. Such parallel processing systems provides large scalability but are mainly used for scientific applications which have large data parallelism. A shared memory multiprocessor system like TICOM is currently used as aserver for the commercial application, however, the shared memory multiprocessor system is known to have very limited scalability. The proposed architecture can support scalability and performance of the parallel processing system while it provides adaptability for the commerical application, hence it can overcome the limitation of the shared memory multiprocessor. The architecture and characteristics of the proposed system shall be described. A proprietary hierarchical crsossbar network is designed for this system, of which the protocol, routing and switching technique and the signal transfer technique are optimized for the proposed architecture. The design trade-offs for the network are described in this paper and with simulation usihng the SES/workbench, it is explored that the network fits to the proposed architecture.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.42 no.6
• /
• pp.19-28
• /
• 2005

The multiprocessor architecture is a good method to improve the computer system performance. The CC-NUMA provides a single shared space with the physically distributed memories is used widely in the multiprocessor computer system. A CC-NUMA has the full-mapped directory for the shared memory md uses a remote cache memory for tile fast memory access. In this paper, we propose a processing node architecture for a CC-NUMA system and a cache coherency protocol on the physically distributed but logically shared system. We show an implementation result of the system which is adopted the cache coherency protocol.

• ETRI Journal
• /
• v.10 no.3
• /
• pp.83-91
• /
• 1988

This paper describes the architecture and the performance analysis of a multiprocessor system, which is based on the shared memory and single system bus. The system bus provides the pended protocol for the multiprocessor environment. Analyzing the processor utilization, address/data bus utilization and memory conflicts, we use a simulation model. The hit ratio of private cache memory is a major factor on the linear increase of the performance of a shared memory based multiprocessor system.

• Journal of the Korean Institute of Telematics and Electronics
• /
• v.25 no.8
• /
• pp.927-936
• /
• 1988

This paper proposes a pipelined memory access method as a new technique for a bus interface between processors and memories in tightly coupled multiprocessor systems. Since the shared bus is bottle neck of the system, model of pipelined access to memory has been developed. Results of the evaluation by the discrete time Markov model showed a significant improvement of the efficiency.

• Journal of the Korea Society for Simulation
• /
• v.8 no.1
• /
• pp.35-49
• /
• 1999

The CC-NUMA based, distributed shared memory is an emerging architecture for multiprocessor computer systems because of its scalability and easy of programming. In this paper, we analyzed performance of a ring-based, CC-NUMA multiprocessor computer system using a commercial workload targeted for popular OLTP applications. Based on the traces collected from real machines, the characteristics of the commercial workload could be obtained. The simulation results showed that the bottleneck on the ring could be effectively removed by using a dual ring structure. We believe our simulation methodology and results will help us to design better multiprocessor computer systems for commercial application domains.

• The KIPS Transactions:PartA
• /
• v.8A no.4
• /
• pp.419-428
• /
• 2001

Advances in circuit and integration technology are continuously boosting the speed of processors. One of the main challenges presented by such developments is the effective use of powerful processors in shared memory multiprocessor system. We believe that the interconnection problem is not solved even for small scale shared memory multiprocessor, since the speed of shared buses is unlikely to keep up with the bandwidth requirements of new powerful processors. In the past few years, point-to-point unidirectional connection have emerged as a very promising interconnection technology. The single slotted ring is the simplest form point-to-point interconnection. The main limitation of the single slotted ring architecture is that latency of access increase linearly with the number of the processors in the ring. Because of this, we proposed the dual slotted ring as an alternative to single slotted ring for cache-based multiprocessor system. In this paper, we analyze the proposed dual slotted ring architecture using new snooping protocol and enforce simulation to compare it with single slotted ring.

• Journal of Electrical Engineering and information Science
• /
• v.2 no.3
• /
• pp.105-112
• /
• 1997

The performance of a shared memory multiprocessor system is very sensitive to process scheduling. w can enhance the performance of a whole system as well as of an individual process by taking the multiprocessor characteristics into account in the design of the process scheduler. In this paper, we proposed a general purpose scheduler for a shared memory multiprocessor, called the Two-Level Multi-Scan (TLMS) process scheduler, that considers the processor affinity loosely and decreases the interference among multiple processors greatly. The TLMS scheduler is composed of a local scheduler at each processor and a semi-global scheduler that balances the load among processors. In particular, the semi-global scheduler tries to minimize priority inversion, which is an important factor of the system performance. The TLMS scheduler also tries to reduce the number of resources to be shared and improves the processor utilization. to meet these requirements, th semi-global scheduler interacts with the operation of the local scheduler when a need arises, thus the name is loose processor-affinity. We also show that the proposed scheduling technique can be extended for other types of resources making it a general purpose resource management queue.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.37B no.11
• /
• pp.1041-1049
• /
• 2012

The transactional memory was proposed to solve the problems of the conventional lock-based synchronization methods in the shared memory multiprocessor system. Various implementation methods for putting the high performance transactional memory to practical use have been continuously studied. However, these studies focus only on the commercialization and performance enhancement of the transactional memory. Besides, there have been few studies to analyze the system overhead of the transactional memory according to the conflict management policy. Thus this paper classifies hardware transactional memory, which is one kind of transactional memories, into four types according to the conflict management policy, and then compares and analyzes their performance and system bus traffic through their modeling and simulation. In addition, the most effective conflict management policy for the hardware transactional memory is presented through these comparison and analysis.

• Journal of KIISE:Computer Systems and Theory
• /
• v.30 no.3_4
• /
• pp.194-204
• /
• 2003

The performance of a shared memory multiprocessor system is dependent on the system software such as scheduling policy as well as hardware system. Most of existing simulators, however, do not support simulation for multi-programmed environment because they can execute only a single benchmark application at a time. We propose a multi-programmed simulation method on a program-driven simulator, which enables the concurrent executions of multiple parallel workloads contending for limited system resources. Using the proposed method, system developers can measure and analyze detailed effects of resource conflicts among the concurrent applications as well as the effects of scheduling policies on a program-driven simulator. As a result, the proposed multi-programmed simulation provides more accurate and realistic performance projection to design a multiprocessor system.

• Electronics and Telecommunications Trends
• /
• v.13 no.5 s.53
• /
• pp.11-22
• /
• 1998

Recently, scalable multiprocessor systems are actively developed for general-purpose computing, which are based on distributed shared memory (DSM) architecture to boost up both programmability and scalability. In this paper, we survey and analyze cache coherence protocols in non-uniform memory access (NUMA) multiprocessor systems. In particular, it has been easily inferred that specialized hardware suitable for NUMA multiprocessor systems with commodity symmetric multiprocessors (SMPs) is highly required. The cache coherence protocol combined with specialized hardware can significantly improve the performance and scalability of NUMA multiprocessor systems, providing better programmability.