• Korean Management Science Review
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• v.31 no.3
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• pp.113-130
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• 2014

Cooperative coevolutionary algorithm (CCEA) has proven to be a very powerful means of solving optimization problems through problem decomposition. CCEA implies the use of several populations, each population having the aim of finding a partial solution for a component of the considered problem. Populations evolve separately and they interact only when individuals are evaluated. Interactions are made to obtain complete solutions by combining partial solutions, or collaborators, from each of the populations. In this respect, we can think of various interaction modes. The goal of this research is to develop a CCEA for a supply chain network design (SCND) problem and identify which interaction mode gives the best performance for this problem. We present general design principle of CCEA for the SCND problem, which require several co-evolving populations. We classify these populations into two groups and classify the collaborator selection scheme into two types, the random-based one and the best fitness-based one. By combining both two groups of population and two types of collaborator selection schemes, we consider four possible interaction modes. We also consider two modes of updating populations, the sequential mode and the parallel mode. Therefore, by combining both four possible interaction modes and two modes of updating populations, we investigate seven possible solution algorithms. Experiments for each of these solution algorithms are conducted on a few test problems. The results show that the mode of the best fitness-based collaborator applied to both groups of populations combined with the sequential update mode outperforms the other modes for all the test problems.

• Journal of Internet Computing and Services
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• v.20 no.3
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• pp.85-92
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• 2019

In this paper, we extract the quantitative relation data of activities from the workflow event log file recorded in the XES standard format and connect them to rediscover the workflow process model. Extract the workflow process patterns and proportions with the rediscovered model. There are four types of control-flow elements that should be used to extract workflow process patterns and portions with log files: linear (sequential) routing, disjunctive (selective) routing, conjunctive (parallel) routing, and iterative routing patterns. In this paper, we focus on four of the factors, disjunctive routing, and conjunctive path. A framework implemented by the authors' research group extracts and arranges the activity data from the log and converts the iteration of duplicate relationships into a quantitative value. Also, for accurate analysis, a parallel process is recorded in the log file based on execution time, and algorithms for finding and eliminating information distortion are designed and implemented. With these refined data, we rediscover the workflow process model following the relationship between the activities. This series of experiments are conducted using the Large Bank Transaction Process Model provided by 4TU and visualizes the experiment process and results.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4C
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• pp.283-289
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• 2005

In this paper, we propose two efficient symbol detection algorithms for space-frequency OFDM (SF-OFDM) transmit diversity scheme. When the number of sub-carriers in SF-OFBM scheme is small, the interference between adjacent sub-carriers may be generated. The proposed algorithms eliminate this interference in a parallel or sequential manlier and achieve a considerable performance improvement over the conventional detection algorithm. The bit error rate (BER) performance of the proposed detection algorithms is evaluated by the simulation. In the case of 2 transmit and 2 receive antennas, at $BER=10^{-4}$ the proposed algorithms achieve the gain improvement of about 3 dB. The symbol detectors with the proposed algorithms are designed in a hardware description language and synthesized to gate-level circuits with the $0.18{\mu}m$ 1.8V CMOS standard cell library. With the division-free architecture, the proposed SF-OFDM-PIC and SF-OFDM-SIC symbol detectors can be implemented using 140k and 129k logic gates, respectively.

• Proceedings of the Korea Information Processing Society Conference
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• 2001.10a
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• pp.767-770
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• 2001

Edge detection is one of issues with essential importance in the area of image process. An edge in image is a boundary or contour which a significant change occurs in image intensity. In the paper, we process edge detection algorithms which are based on Potts automata. The dynamical behavior of these automata is completely determined by Lyapunov operators for sequential and parallel update. If Potts Automata convergence to fixed points, then it can be used to image processing. From the generalized Potts automata point of view, we propose a Potts Automata technique for detecting edge. Based on the experimental results we discuss the advantage and efficiency.

• KIPS Transactions on Computer and Communication Systems
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• v.7 no.9
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• pp.219-226
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• 2018

One of the systematic ways to generate the number of all cases is a combination to construct a combination tree, and its time complexity is O($2^n$). A combination tree is used for various purposes such as the graph homogeneity problem, the initial model for calculating frequent item sets, and so on. However, algorithms that must search the number of all cases of a combination are difficult to use realistically due to high time complexity. Nevertheless, as the amount of data becomes large and various studies are being carried out to utilize the data, the number of cases of searching all cases is increasing. Recently, as the GPU environment becomes popular and can be easily accessed, various attempts have been made to reduce time by parallelizing algorithms having high time complexity in a serial environment. Because the method of generating the number of all cases in combination is sequential and the size of sub-task is biased, it is not suitable for parallel implementation. The efficiency of parallel algorithms can be maximized when all threads have tasks with similar size. In this paper, we propose a method to efficiently collaborate between CPU and GPU to parallelize the problem of finding the number of all cases. In order to evaluate the performance of the proposed algorithm, we analyze the time complexity in the theoretical aspect, and compare the experimental time of the proposed algorithm with other algorithms in CPU and GPU environment. Experimental results show that the proposed CPU and GPU collaboration algorithm maintains a balance between the execution time of the CPU and GPU compared to the previous algorithms, and the execution time is improved remarkable as the number of elements increases.

• Journal of the Korea Society of Computer and Information
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• v.27 no.2
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• pp.1-8
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• 2022

In this paper, we design and implement a GPU-based parallel algorithm to effectively solve the traveling salesman problem through an ant color system. The repetition process of generating hundreds or thousands of tours simultaneously in TSP utilizes GPU's task-level parallelism, and the update process of pheromone trails data actively exploits data parallelism by 32x32 thread blocks. In particular, through simultaneous memory access of multiple threads, the coalesced accesses on continuous memory addresses and concurrent accesses on shared memory are supported. This experiment used 127 to 1002 city data provided by TSPLIB, and compared the performance of sequential and parallel algorithms by using Intel Core i9-9900K CPU and Nvidia Titan RTX system. Performance improvement by GPU parallelization shows speedup of about 10.13 to 11.37 times.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1537-1545
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• 1993

In this paper, we design a pattern generator and a fault position detector to implement the proposed fault test algorithms which are Column Weight Sensitive Fault (CWSF) test algorithm and bit line decoder fault test algorithm for performing the Built-In Self Test(BIST) in RAM. A pattern generator consists of an address generator and a data generator. An address generator is divided into a row address generator for effective address and a column address generator for sequential and parallel addresses. A fault position detector is designed to determine whether full occurred or not and to find the position of the fault. We verify the implemented circuits by the simulation.

• ETRI Journal
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• v.43 no.2
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• pp.260-271
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• 2021

This paper addresses Very large-scale integration (VLSI) placement optimization, which is important because of the rapid development of VLSI design technologies. The goal of this study is to develop a hybrid algorithm for VLSI placement. The proposed algorithm includes a sequential combination of a genetic algorithm and an evolutionary algorithm. It is commonly known that local search algorithms, such as random forest, hill climbing, and variable neighborhoods, can be effectively applied to NP-hard problem-solving. They provide improved solutions, which are obtained after a global search. The scientific novelty of this research is based on the development of systems, principles, and methods for creating a hybrid (combined) placement algorithm. The principal difference in the proposed algorithm is that it obtains a set of alternative solutions in parallel and then selects the best one. Nonstandard genetic operators, based on problem knowledge, are used in the proposed algorithm. An investigational study shows an objective-function improvement of 13%. The time complexity of the hybrid placement algorithm is O(N2).

• Journal of Internet Computing and Services
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• v.2 no.4
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• pp.91-99
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• 2001

Since roost of the program execution time is spent in the loop structure, the problem of extracting parallelism from sequential loop has been one of the most important research issues. However. roost programs have Implicit interprocedure parallelism. This paper presents a generalized method extracting parallelism in loops having the procedure calls. Most parallelization of loops having procedure calls focus on the uniform code where data dependency distance is constant. We present algorithms which can be applied to uniform code, nonuniform code, and complex code. The performance of the proposed algorithm, loop extraction, loop embedding and procedure cloning transformation methods have been evaluated using CRAY-T3E. The result shows the effective of the proposed algorithm.

• The KIPS Transactions:PartD
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• v.8D no.4
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• pp.347-360
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• 2001

The most expensive spatial operation in spatial databases is a spatial join which computes a combined table of which tuple consists of two tuples of the two tables satisfying a spatial predicate. Although the execution time of sequential processing of a spatial join has been so far considerably improved, the response time is not tolerable because of not meeting the requirements of interactive users. It is usually appropriate to use parallel processing to improve the performance of spatial join processing. However, as the number of processors increases, the efficiency of each processor decreases rapidly because of the disk bottleneck and the overhead of message passing. This paper proposes the method of task allocation to soften the disk bottleneck caused by accessing the shared disk at the same time, and to minimize message passing among processors. In order to evaluate the performance of the proposed method in terms of the number of disk accesses and message passing, we conduct experiments on the two kinds of parallel spatial join algorithms. The experimental tests on the MIMD parallel machine with shared disks show that the proposed semi-dynamic task allocation method outperforms the static and dynamic task allocation methods.