• Journal of the Korea Society for Simulation
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• v.14 no.4
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• pp.55-68
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• 2005

The advancement in semiconductor technology is leading toward smaller critical dimension designs and larger wafer manufactures. Due to such phenomena, semiconductor industry is in need of an accurate control of the process. Photolithography is one of the key processes where the pattern of each layer is formed. In this process, precise superposition of the current layer to the previous layer is critical. Therefore overlay parameters of the semiconductor photolithography process is targeted for this research. The complex relationship among the input parameters and the output metrologies is difficult to understand and harder yet to model. Because of the superiority in modeling multi-nonlinear relationships, neural networks is used for the simulator modeling. For training the neural networks, conjugate gradient method is employed. An experiment is performed to evaluate the performance among the proposed neural network simulator, stepwise regression model, and the currently practiced prediction model from the test site.

• International Journal of Precision Engineering and Manufacturing
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• v.5 no.3
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• pp.11-18
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• 2004

In this paper, the classification of artificial defects in semiconductor packages is studied by using pattern recognition technology. For this purpose, the pattern recognition algorithm includes the user made MATLAB code. And preprocess is made of the image process and self-organizing map, which is the input of the back-propagation neural network and the dimensionality reduction method, The image process steps are data acquisition, equalization, binary and edge detection. Image process and self-organizing map are compared to the preprocess method. Also the pattern recognition technology is applied to classify two kinds of defects in semiconductor packages: cracks and delaminations.

• Journal of Industrial Technology
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• v.43 no.1
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• pp.49-55
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• 2023

Cluster tools are extensively employed in various wafer fabrication processes within the semiconductor manufacturing industry, including photo lithography, etching, and chemical vapor deposition. Contemporary fabrication facilities encounter customer orders with technical specifications that are similar yet slightly varied. Consequently, modern fabrications concurrently manufacture two or three different wafer types using a cluster tool to maximize chamber utilization and streamline the flow of wafer lots between different process stages. In this review, we introduce two methods of concurrent processing of multiple wafer types: 1) concurrent processing of multiple wafer types with different job flows, 2) concurrent processing of multiple wafer types with identical job flows. We describe relevant research trends and achievements and discuss future research directions.

• Journal of the Semiconductor & Display Technology
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• v.12 no.1
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• pp.47-51
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• 2013

The screen printing is a process that is widely used in manufacturing process of various fields such as flexible devices, portable multimedia devices, OLED, and the solar cell. The screen printing method has been studied as a method for forming the high precision micro-pattern, making the low-cost manufacturing process and reducing cost through improvement of productivity. It is applicable to deposit and forming the pillars which are one of the core element for comprising vacuum glazing. In this paper, by using the paste of the glass frit base, the screen printing was performed. We analyzed the effect for the printing process to deposit pillar paste on the screen printing parameters by the factorial experimental design. The polynomial predicting the volume of the printed supporting pillars was drawn by using screen printing.

• Journal of the Semiconductor & Display Technology
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• v.15 no.1
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• pp.17-21
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• 2016

EUV (Extreme Ultraviolet) pellicle which protects a mask from contamination became a critical issue for the application of EUV lithography to high-volume manufacturing. However, researches of EUV pellicle are still delayed due to no typical manufacturing methods for large-scale EUV pellicle. In this study, EUV pellicle membrane manufacturing method using not only KOH (potassium hydroxide) wet etching process but also a water bath was suggested for uniform etchant temperature distribution. KOH wet etching rates according to KOH solution concentration and solution temperature were confirmed and proper etch condition was selected. After KOH wet etching condition was set, $5cm{\times}5cm$ SiNx (silicon nitride) pellicle membrane with 80% EUV transmittance was successfully manufactured. Transmittance results showed the feasibility of wet etching method with water bath as a large-scale EUV pellicle manufacturing method.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.37 no.5
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• pp.527-532
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• 2024

Physically Unclonable Functions (PUFs) provide a high level of security for private keys using unique physical characteristics of hardware. However, fabricating PUF chips requires numerous semiconductor processes, leading to high costs, which limits their applications. In this work, we introduce a low-cost manufacturing method for PUF security chips. First, surface roughening through wet-etching is utilized to create random variables. Additionally, physical vapor deposition is added to further enhance randomness. After PUF chip fabrication, both Hamming distance (HD) and Hamming weight (HW) are extracted and compared to verify the fabricated chip. It is confirmed that the PUF chip using two different multiple process variables demonstrates superior uniqueness and uniformity compared to the PUF security chip fabricated using only a single process variable.

• Journal of the Semiconductor & Display Technology
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• v.23 no.2
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• pp.135-142
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• 2024

Cu-Cu bonding, one of the key technologies in advanced packaging, enhances semiconductor chip performance, miniaturization, and energy efficiency by facilitating rapid data transfer and low power consumption. However, the quality of the interface bonding can significantly impact overall bond quality, necessitating strategies to quickly detect and classify in-process defects. This study presents a methodology for detecting defects in wafer junction areas from Scanning Acoustic Microscopy images using a ResNet-50 based deep learning model. Additionally, the use of the defect map is proposed to rapidly inspect and categorize defects occurring during the Cu-Cu bonding process, thereby improving yield and productivity in semiconductor manufacturing.

• Journal of East Asia Management
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• v.3 no.2
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• pp.43-64
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• 2022

Exploring innovations for latecomers to catch up has been a popular concern in industry and academia. Over the last decade, more and more East Asian latecomer firms have moved beyond imitation and are delivering innovative products and services to the market. However, the semiconductor latecomers from China have limited success in catching up with more mature semiconductor firms. Our study examines how semiconductor latecomers to break through the latecomer's dilemma by innovation and achieve catch-up. We use a single-case approach for the Semiconductor Manufacturing International Corporation (SMIC) vertical development process to analysis its innovation path of catching up. The study's results showed that SMIC relied on the government's policy and funding support, and based on the strategic endurance of entrepreneurs, it persisted in technology R&D investment and independent innovation for 20 years. SMIC finally smashed the dilemma of latecomers and successfully achieved catch-up. With these findings, we believe that the path of catching up innovation for semiconductor latecomers should be equipped with independent innovation of technology, strategic leadership of entrepreneurs and support of government policies. As these factors are combined, latecomer firms' position is expected to rise and catch-up will become visible. Our study contributes to some enlightenment on the innovation path for latecomers in China and global semiconductors to achieve their catch-up.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.11a
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• pp.15-18
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• 2002

To achieve the global planarization, CMP Technology has been used to the next generation semiconductor process, and the study made tremendous progress up to date. As the device demension shrinked， CMP Technology has been applied in a various way and more people interested in this field to simplify the process. To attain the goal for safer 0.13um or below 10 nano process, many of those expected task must be solved. By describing this current CMP process issue and future trend for the CMP planarization process, It personally hope that this paper would help to the people who has concerns for the next generation semiconductor manufacturing industry in common.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1995.10a
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• pp.411-414
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• 1995

Statistical Process Control (SPC) is a set of methodologies for signaling the presence of undesired sources of variation in manufacturing processes. Expert System in SPC can serve as a valuable tool to automate the analysis and interpretation of control charts. In this paper we put forward a method of successful application of Expert System to SPC in manufacturing process.