• Journal of the Semiconductor & Display Technology
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• v.5 no.4 s.17
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• pp.17-22
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• 2006

In the manufacturing processes of semiconductor, test process is important for quality of products. In the manufacturing process of dynamic memory, memory test is more important. So, automatic test equipment(ATE) is used necessarily. But, according to increase of speed of dynamic memory operation, the rapid test equipment is needed. Impedance matching between ATE and dynamic memory is expected to be an important problem for making a rapid test equipment over 1Gbps. According to increase of speed, inner impedance of ATE also works on important parameter for test. This paper is about the method that is for impedance matching of inner impedance and coaxial cable occurring in manufacturing of ATE. We proved effects of inner impedance by electric theory and verified the method of impedance matching using computer simulation.

• Journal of the Semiconductor & Display Technology
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• v.19 no.4
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• pp.121-125
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• 2020

With miniaturization of semiconductor, the manufacturing process become more complex, and undetected small changes in the state of the equipment have unexpectedly changed the process results. Fault detection classification (FDC) system that conducts more active data analysis is feasible to achieve more precise manufacturing process control with advanced machine learning method. However, applying machine learning, especially in supervised learning criteria, requires an arduous data labeling process for the construction of machine learning data. In this paper, we propose a semi-supervised learning to minimize the data labeling work for the data preprocessing. We employed equipment status variable identification (SVID) data and optical emission spectroscopy data (OES) in silicon etch with SF6/O2/Ar gas mixture, and the result shows as high as 95.2% of labeling accuracy with the suggested semi-supervised learning algorithm.

• Journal of the Korea Society for Simulation
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• v.15 no.2
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• pp.51-57
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• 2006

Production environment of semiconductor industry is shifting from 200mm wafer process to 300mm wafer process. In the new era of semiconductor industry, FAB (fabrication) Line Automation is a key issue that semiconductor industry is facing in shifting from 200mm wafer fabrication to 300mm wafer fabrication. In addition, since the semiconductor manufacturing technologies are being widely spread and market competitions are being stiffened, cost-down techniques became basis of growth. Most companies are trying to reduce average cycle time to increase productivity and delivery time. In this paper, we simulated 300mm wafer fabrication semiconductor manufacturing process by laying great emphasis on reduce average cycle time.

• Proceedings of the Korea Society for Simulation Conference
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• 2002.11a
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• pp.115-121
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• 2002

The growth of semiconductor industry attracted to researchers like design, facility technique and making small size chip areas. But nowadays, cause of technology extension and oversupply and price down, yield improvement is the most important point on growth. This paper describes the computer mode]ing technique as the solutions to analyze the problem, to formalize the semiconductor manufacturing process and to build advanced manufacturing environments. The computer models are built referring an existing 8' wafer production line in Korea.

• The Korean Journal of Applied Statistics
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• v.34 no.1
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• pp.99-114
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• 2021

With the Fourth Industrial Revolution based on new technology, the semiconductor manufacturing industry researches various analysis methods such as detecting process abnormalities and predicting yield based on equipment sensor data generated in the manufacturing process. The semiconductor manufacturing process consists of hundreds of processes and thousands of measurement processes associated with them, each of which has properties that cannot be defined by chemical or physical equations. In the individual measurement process, the actual measurement ratio does not exceed 0.1% to 5% of the target product, and it cannot be kept constant for each measurement point. For this reason, efforts are being made to determine whether to manage by using equipment sensor data that can indirectly determine the normal state of each step of the process. In this study, the Functional Data Analysis (FDA) was proposed to define a process abnormality detection process based on equipment sensor data and compensate for the disadvantages of the currently applied statistics-based diagnosis method. Anomaly detection accuracy was compared using machine learning on actual field case data, and its effectiveness was verified.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.12 no.5
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• pp.163-169
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• 2013

The objective of this study is to replace labor intensive forging processes by an automated system. For achieving it, an exclusive mechanism that consists of a positioner, an arm, and a hanger is configured to handle hot forging objects. Also, a structural analysis is applied to the horizontal motion unit, which is the most highly loaded, in order to verify its validity. In addition, its possibility is also verified through identifying the performance of the proposed system before applying it to sites. As a result, the major characteristic items, such as positioning accuracy, material diameter, object traveling weight, product failure rate, and forging process rate, in this system are perfectly verified for applying it to manufacturing sites.

• The Journal of Korea Institute of Information, Electronics, and Communication Technology
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• v.14 no.4
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• pp.275-283
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• 2021

In this study, a driver IC for an AC-powered LED that can be manufactured with a low voltage semiconductor process is designed and the performances of the driver IC were simulated. In order to manufacture a driver IC that operates directly at AC 220V, a semiconductor manufacturing process that satisfies a breakdown voltage of 500V or higher is required. A semiconductor manufacturing process for a high-voltage device requires a much higher manufacturing cost than a general semiconductor process for a low-voltage device. Therefore, the LED driver IC is designed in series so that it can be manufactured with semiconductor process technology that implements a low-voltage device. This makes it possible to divide and apply the voltage to each LED block even if the input voltage is high. The LED lighting circuit shows a power factor of 96% at 220V. In the pnp transistor circuit, a very high power factor of 99.7% can be obtained, and it shows a very stable operation regardless of the fluctuation of the input voltage.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.67 no.3
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• pp.474-478
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• 2018

The use of metals such as aluminum and titanium and the related industrial facilities have been continuously increasing to meet the requirements of the improvement of high-tech products due to the development of industry, and explosion of metal dust. Semiconductor process Metal dust is essential, but research is insufficient. The purpose of this study is to identify risk by analyzing the quantitative risk such as maximum explosion pressure and minimum explosion concentration applied international test standard in order to select the semiconductor process facilities handling dust and to predict possible risk of accidents.

• Journal of the Semiconductor & Display Technology
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• v.14 no.1
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• pp.45-49
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• 2015

Process gases with vapor or liquid phase as well as gas phase may experience alteration in itself or be contaminated in the fluid pipe to the process chamber. And thus it result in as particles or defects on the substrates in semiconductor, LCD, LED manufacturing. Purifiers and filters are used for control of contamination. However, none of detection device is available in the delivery line. In this paper, we propose simple device with lighting and sensing in order to predict contamination of the fluid or the tube wall. For some general purpose gases, it showed constant voltage output regardless of the flow rates. But, the smoke and the moisture in the air lowered the figure due to its concentration. Numerical values for several solid and liquid media were obtained. And, the operating temperature tendency was investigated.

• Journal of the Semiconductor & Display Technology
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• v.22 no.2
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• pp.56-63
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• 2023

This paper presents a method using finite element analysis and topology optimization to address the issue of overdesign in pressure-explosion proof enclosure doors for semiconductor manufacturing processes. The design conducted in this paper focuses on the pattern design of the enclosure door and its fixation components. The process consists of a solid-filled model, a topology optimization model, and a post-processing model. By applying environmental conditions to each model and comparing the maximum displacement, maximum equivalent stress, and weight values, it was confirmed that a reduction of about 13% in weight is achievable.