• Journal of the Korean Institute of Telematics and Electronics
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• v.20 no.4
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• pp.10-15
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• 1983

In this paper effective methods of demodulation and equalization in a 9600 bps modem have been studied. To reduce the number of multiplications required per symbol in demodula-tion, the method of using a decimation filter is presented. In the equalizer the optimum step size and the steady state mean-squared error (MSE) are obtained from computer simulation results. The performance of the first-order carrier phase tracking loop is compared with that of the second-order loop when carrier frequency offset exists. In addition, the finite word length effects in the equalizer are studied.

• Journal of Advanced Navigation Technology
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• v.1 no.1
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• pp.70-80
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• 1997

In this paper, the performances of two noncoherent code tracking loops, i. e., traditional code tracking loop(TCTL) and modified code tracking loop(MCTL) are analyzed and compared in a CDMA mobile environment. Closed-form formulas for steady-state jitter variance are derived analytically for the two schemes as a function of the pulse shaping filter, timing offset, signal-to-interference ratio, and loop bandwidth. The design issues of the loop filter are also addressed with emphasis on the second-order tracking loop. Finally, the degradation of BER performance due to timing errors is examined in a CDMA reverse link for IMT-2000 designed by ETRI.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.4
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• pp.857-864
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• 1998

The infuluence of Doppler effects on the tracking performance of a noncoherent second-order delay locked loop (DLL) operating on a data modulated signal is investigated. For the perfoermance analysis we consider the tracking accuracy (steady state error and jitter) of the linear DLL and the reliability of the nonlinear loop. The nonlinear analysis concerning the loop reliability makes use of an asympototic expansion for the MTLL(mean time to lose lock) which has been derived by applying the singular perturbation method. In particular, we give optimal loop parameters and the optimal bandwidth of the bandpass filter in the loop arms to achieve a maximum MTLL. Since Doppler effects can be producesd comparatively in LEO system, we can espect the more reliable DLL loop design. by using the results of the circuit simulation, the delay lock loop is synthesized in FPGA, and verified to get the GPS data from the STR-2770 GPS simulator system. So, the synthesized logic circuit is shown be accurately performed.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.7
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• pp.1552-1558
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• 2011

In this paper, a dual-loop Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a low power consuming voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF which occupies a large area. The proposed dual-loop P DLL can have a small gain VCDL by controlling the magnitude of capacitor and charge pump current on the loop of VCDL. The proposed dual-loop P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by Hspice simulation.

• Journal of Communications and Networks
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• v.8 no.1
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• pp.8-12
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• 2006

Master-slave (M-S) strategies implemented with chain circuits are the main option in order to distribute clock signals along synchronous networks in several telecommunication and control applications. Here, we study the two types of masterslave chains: Without clock feedback, i.e., one-way master-slave (OWMS) and with clock feedback, i.e., two-way master-slave (TWMS) considering the slave nodes as second-order phase-locked loops (PLL) for several types of loop low-pass filters.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.6
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• pp.51-56
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• 2010

In this paper, a novel Integer-N phase-delay locked loop(P DLL) architecture has been proposed using a voltage controlled delay line(VCDL). The P DLL can have the LF of one small capacitance instead of the conventional second or third-order LF. The size of chip is $255{\mu}m$ $\times$ $935.5{\mu}m$ including the LF. The proposed P DLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.4A
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• pp.429-438
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• 2004

In this paper, a decision-feedback coherent code tracking loop is designed for WCDMA systems and its performance is analyzed in terms of jitter variance considering the effect of phase and symbol estimation errors for both AWGN and fading environments. An analytical closed-form formula for jitter variance is Int derived for AWGN environments as a function of a pulse-shaping filter, timing offset, signal-to-interference ratio, and loop bandwidth while involving the phase estimation error and bit error rate, and the upper bound of jitter variance is derived for fading environments. Finally a second-order coherent code tracking loop is designed with the DPCH frame format #13 of the WCDHA forward link selected as a target system, and its performance is evaluated by the closed-form formula and compared with the simulation results for both AWGN and Rayleigh fading environments.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.43 no.3 s.309
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• pp.1-7
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• 2006

In this paper, a method for IMC-PID controller tuning is proposed based on obtaining a controller from closed-loop transfer function. It is considered a plant with the second-order plus dead time(SOPDT) model and selected the third-order plus dead time transfer function model as a target function. The filter function is derived from the suitable target function to satisfy the design specifications. A robustness test was done to verify the robust-stability.

• International Journal of Aeronautical and Space Sciences
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• v.18 no.3
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• pp.565-573
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• 2017

This paper presents a multistage in-flight alignment (MIFA) method for a strapdown inertial navigation system (SDINS) suitable for moving vehicles with no initial attitude references. A SDINS mounted on a moving vehicle frequently loses attitude information for many reasons, and it makes solving navigation equations impossible because the true motion is coupled with an undefined vehicle attitude. To determine the attitude in such a situation, MIFA consists of three stages: a coarse horizontal attitude, coarse heading, and fine attitude with adaptive Kalman navigation filter (AKNF) in order. In the coarse horizontal alignment, the pitch and roll are coarsely estimated from the second order damping loop with an input of acceleration differences between the SDINS and GPS. To enhance estimation accuracy, the acceleration is smoothed by a scalar filter to reflect the true dynamics of a vehicle, and the effects of the scalar filter gains are analyzed. Then the coarse heading is determined from the GPS tracking angle and yaw increment of the SDINS. The attitude from these two stages is fed back to the initial values of the AKNF. To reduce the estimated bias errors of inertial sensors, special emphasis is given to the timing synchronization effects for the measurement of AKNF. With various real flight tests using an UH60 helicopter, it is proved that MIFA provides a dramatic position error improvement compared to the conventional gyro compass alignment.

• Journal of Power Electronics
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• v.17 no.1
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• pp.262-271
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• 2017

This paper studies the performances of five typical Phase-locked Loops (PLLs) for distorted and unbalanced grid, which are the Decoupled Double Synchronous Reference Frame PLL (DDSRF-PLL), Double Second-Order Generalized Integrator PLL (DSOGI-PLL), Double Second-Order Generalized Integrator Frequency-Lock Loop (DSOGI-FLL), Double Inverse Park Transformation PLL (DIPT-PLL) and Complex Coefficient Filter based PLL (CCF-PLL). Firstly, the principles of each method are meticulously analyzed and their unified small-signal models are proposed to reveal their interior relations and design control parameters. Then the performances are compared by simulations and experiments to investigate their dynamic and steady-state performances under the conditions of a grid voltage with a negative sequence component, a voltage drop and a frequency step. Finally, the merits and drawbacks of each PLL are given. The compared results provide a guide for the application of current control, low voltage ride through (LVRT), and unintentional islanding detection.