• Title/Summary/Keyword: search algorithm

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A Competitive Coevolutionary Algorithm with Tournament Competitions (토너먼트 경쟁에 의한 경쟁 공진화 알고리듬)

  • Kim, Sun-Jin;Kim, Yeo-Keun;Kim, Jae-Yun;Kwak, Jai-Seung
    • Journal of Korean Institute of Industrial Engineers
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    • v.26 no.2
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    • pp.101-109
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    • 2000
  • A competitive coevolutionary algorithm is a probabilistic search method that imitates the biological process that two or more species competitively coevolve through evolutionary arms race. The algorithm has been used to efficiently solve adversarial problems that can be formulated as the search for a solution that is correct over a large space of test cases. We develop an efficient competitive coevolutionary algorithm to solve adversarial problems with high complexity. The algorithm developed in this paper employs three methods: tournament competitions, exchanging of entry fee, and localized coevolution. Analyzed in this paper are the effects of the methods on the performance of the proposed algorithm. The extensive experiments show that our algorithm can progress an evolutionary arms race between competitive coevolving species and then outperforms existing approaches to solving the adversarial problems.

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Heuristic algorithm to raise efficiency in clustering (군집의 효율향상을 위한 휴리스틱 알고리즘)

  • Lee, Seog-Hwan;Park, Seung-Hun
    • Journal of the Korea Safety Management & Science
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    • v.11 no.3
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    • pp.157-166
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    • 2009
  • In this study, we developed a heuristic algorithm to get better efficiency of clustering than conventional algorithms. Conventional clustering algorithm had lower efficiency of clustering as there were no solid method for selecting initial center of cluster and as they had difficulty in search solution for clustering. EMC(Expanded Moving Center) heuristic algorithm was suggested to clear the problem of low efficiency in clustering. We developed algorithm to select initial center of cluster and search solution systematically in clustering. Experiments of clustering are performed to evaluate performance of EMC heuristic algorithm. Squared-error of EMC heuristic algorithm showed better performance for real case study and improved greatly with increase of cluster number than the other ones.

A hybrid CSS and PSO algorithm for optimal design of structures

  • Kaveh, A.;Talatahari, S.
    • Structural Engineering and Mechanics
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    • v.42 no.6
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    • pp.783-797
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    • 2012
  • A new hybrid meta-heuristic optimization algorithm is presented for design of structures. The algorithm is based on the concepts of the charged system search (CSS) and the particle swarm optimization (PSO) algorithms. The CSS is inspired by the Coulomb and Gauss's laws of electrostatics in physics, the governing laws of motion from the Newtonian mechanics, and the PSO is based on the swarm intelligence and utilizes the information of the best fitness historically achieved by the particles (local best) and by the best among all the particles (global best). In the new hybrid algorithm, each agent is affected by local and global best positions stored in the charged memory considering the governing laws of electrical physics. Three different types of structures are optimized as the numerical examples with the new algorithm. Comparison of the results of the hybrid algorithm with those of other meta-heuristic algorithms proves the robustness of the new algorithm.

Design of Genetic Algorithm-based Parking System for an Autonomous Vehicle

  • Xiong, Xing;Choi, Byung-Jae
    • International Journal of Fuzzy Logic and Intelligent Systems
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    • v.9 no.4
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    • pp.275-280
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    • 2009
  • A Genetic Algorithm (GA) is a kind of search techniques used to find exact or approximate solutions to optimization and searching problems. This paper discusses the design of a genetic algorithm-based intelligent parking system. This is a search strategy based on the model of evolution to solve the problem of parking systems. A genetic algorithm for an optimal solution is used to find a series of optimal angles of the moving vehicle at a parking space autonomously. This algorithm makes the planning simpler and the movement more effective. At last we present some simulation results.

Gamma ray interactions based optimization algorithm: Application in radioisotope identification

  • Ghalehasadi, Aydin;Ashrafi, Saleh;Alizadeh, Davood;Meric, Niyazi
    • Nuclear Engineering and Technology
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    • v.53 no.11
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    • pp.3772-3783
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    • 2021
  • This work proposes a new efficient meta-heuristic optimization algorithm called Gamma Ray Interactions Based Optimization (GRIBO). The algorithm mimics different energy loss processes of a gamma-ray photon during its passage through a matter. The proposed novel algorithm has been applied to search for the global minima of 30 standard benchmark functions. The paper also considers solving real optimization problem in the field of nuclear engineering, radioisotope identification. The results are compared with those obtained by the Particle Swarm Optimization, Genetic Algorithm, Gravitational Search Algorithm and Grey Wolf Optimizer algorithms. The comparisons indicate that the GRIBO algorithm is able to provide very competitive results compared to other well-known meta-heuristics.

Fast Multi-Resolution Exhaustive Search Algorithm Based on Clustering for Efficient Image Retrieval (효율적인 영상 검색을 위한 클러스터링 기반 고속 다 해상도 전역 탐색 기법)

  • Song, Byeong-Cheol;Kim, Myeong-Jun;Ra, Jong-Beom
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.38 no.2
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    • pp.117-128
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    • 2001
  • In order to achieve optimal retrieval, i.e., to find the best match to a query according to a certain similarity measure, the exhaustive search should be performed literally for all the images in a database. However, the straightforward exhaustive search algorithm is computationally expensive in large image databases. To reduce its heavy computational cost, this paper presents a fast exhaustive multi-resolution search algorithm based on image database clustering. Firstly, the proposed algorithm partitions the whole image data set into a pre-defined number of clusters having similar feature contents. Next, for a given query, it checks the lower bound of distances in each cluster, eliminating disqualified clusters. Then, it only examines the candidates in the remaining clusters. To alleviate unnecessary feature matching operations in the search procedure, the distance inequality property is employed based on a multi-resolution data structure. The proposed algorithm realizes a fast exhaustive multi-resolution search for either the best match or multiple best matches to the query. Using luminance histograms as a feature, we prove that the proposed algorithm guarantees optimal retrieval with high searching speed.

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Deinterlacing Method for improving Motion Estimator based on multi arithmetic Architecture (다중연산구조기반의 고밀도 성능향상을 위한 움직임추정의 디인터레이싱 방법)

  • Lee, Kang-Whan
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.44 no.1
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    • pp.49-55
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    • 2007
  • To improved the multi-resolution fast hierarchical motion estimation by using de-interlacing algorithm that is effective in term of both performance and VLSI implementation, is proposed so as to cover large search area field-based as well as frame based image processing in SoC design. In this paper, we have simulated a various picture mode M=2 or M=3. As a results, the proposed algorithm achieved the motion estimation performance PSNR compare with the full search block matching algorithm, the average performance degradation reached to -0.7dB, which did not affect on the subjective quality of reconstructed images at all. And acquiring the more desirable to adopt design SoC for the fast hierarchical motion estimation, we exploit foreground and background search algorithm (FBSA) base on the dual arithmetic processor element(DAPE). It is possible to estimate the large search area motion displacement using a half of number PE in general operation methods. And the proposed architecture of MHME improve the VLSI design hardware through the proposed FBSA structure with DAPE to remove the local memory. The proposed FBSA which use bit array processing in search area can improve structure as like multiple processor array unit(MPAU).

A Study on Motion Estimator Design Using DCT DC Value (DCT 직류 값을 이용한 움직임 추정기 설계에 관한 연구)

  • Lee, Gwon-Cheol;Park, Jong-Jin;Jo, Won-Gyeong
    • Journal of the Institute of Electronics Engineers of Korea SP
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    • v.38 no.3
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    • pp.258-268
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    • 2001
  • The compression method is necessarily used to send the high quality moving picture that contains a number of data in image processing. In the field of moving picture compression method, the motion estimation algorithm is used to reduce the temporal redundancy. Block matching algorithm to be usually used is distinguished partial search algorithm with full search algorithm. Full search algorithm be used in this paper is the method to compare the reference block with entire block in the search window. It is very efficient and has simple data flow and control circuit. But the bigger the search window, the larger hardware size, because large computational operation is needed. In this paper, we design the full search block matching motion estimator. Using the DCT DC values, we decide luminance. And we apply 3 bit compare-selector using bit plane to I(Intra coded) picture, not using 8 bit luminance signals. Also it is suggested that use the same selective bit for the P(Predicted coded) and B(Bidirectional coded) picture. We compare based full search method with PSNR(Peak Signal to Noise Ratio) for C language modeling. Its condition is the reference block 8$\times$8, the search window 24$\times$24 and 352$\times$288 gray scale standard video images. The result has small difference that we cannot see. And we design the suggested motion estimator that hardware size is proved to reduce 38.3% for structure I and 30.7% for structure II. The memory is proved to reduce 31.3% for structure I and II.

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Hardware Accelerated Design on Bag of Words Classification Algorithm

  • Lee, Chang-yong;Lee, Ji-yong;Lee, Yong-hwan
    • Journal of Platform Technology
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    • v.6 no.4
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    • pp.26-33
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    • 2018
  • In this paper, we propose an image retrieval algorithm for real-time processing and design it as hardware. The proposed method is based on the classification of BoWs(Bag of Words) algorithm and proposes an image search algorithm using bit stream. K-fold cross validation is used for the verification of the algorithm. Data is classified into seven classes, each class has seven images and a total of 49 images are tested. The test has two kinds of accuracy measurement and speed measurement. The accuracy of the image classification was 86.2% for the BoWs algorithm and 83.7% the proposed hardware-accelerated software implementation algorithm, and the BoWs algorithm was 2.5% higher. The image retrieval processing speed of BoWs is 7.89s and our algorithm is 1.55s. Our algorithm is 5.09 times faster than BoWs algorithm. The algorithm is largely divided into software and hardware parts. In the software structure, C-language is used. The Scale Invariant Feature Transform algorithm is used to extract feature points that are invariant to size and rotation from the image. Bit streams are generated from the extracted feature point. In the hardware architecture, the proposed image retrieval algorithm is written in Verilog HDL and designed and verified by FPGA and Design Compiler. The generated bit streams are stored, the clustering step is performed, and a searcher image databases or an input image databases are generated and matched. Using the proposed algorithm, we can improve convenience and satisfaction of the user in terms of speed if we search using database matching method which represents each object.

A Hierarchical Packet Classification Algorithm Using Set-Pruning Binary Search Tree (셋-프루닝 이진 검색 트리를 이용한 계층적 패킷 분류 알고리즘)

  • Lee, Soo-Hyun;Lim, Hye-Sook
    • Journal of KIISE:Information Networking
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    • v.35 no.6
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    • pp.482-496
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    • 2008
  • Packet classification in the Internet routers requires multi-dimensional search for multiple header fields for every incoming packet in wire-speed, hence packet classification is one of the most important challenges in router design. Hierarchical packet classification is one of the most effective solutions since search space is remarkably reduced every time a field search is completed. However, hierarchical structures have two intrinsic issues; back-tracking and empty internal nodes. In this paper, we propose a new hierarchical packet classification algorithm which solves both problems. The back-tracking is avoided by using the set-pruning and the empty internal nodes are avoided by applying the binary search tree. Simulation result shows that the proposed algorithm provides significant improvement in search speed without increasing the amount of memory requirement. We also propose an optimization technique applying controlled rule copy in set-pruning.