• Journal of Computing Science and Engineering
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• v.5 no.3
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• pp.269-281
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• 2011

STEPSTONE is a joint industry-university project to create open source technology that would enable the scalable, "friction-free" integration of device-based healthcare solutions into enterprise systems using a Service Oriented Architecture (SOA). Specifically, STEPSTONE defines a first proposal to a Service Oriented Device Architecture (SODA) framework, and provides for initial reference implementations. STEPSTONE also intends to encourage a broad community effort to further develop the framework and its implementations. In this paper, we present SODA, along with two implementation proposals of SODA's device integration. We demonstrate the ease by which SODA was used to develop an end-to-end personal healthcare monitoring system. We also demonstrate the ease by which the STEPSTONE system was extended by other participants - Washington State University - to include additional devices and end user interfaces. We show clearly how SODA and therefore SODA devices make integration almost automatic, replicable, and scalable. This allows telehealth system developers to focus their energy and attention on the system functionality and other important issues, such as usability, privacy, persuasion and outcome assessment studies.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.25 no.10B
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• pp.1675-1689
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• 2000

We present CReMeS a CORBA-compliant design and implementation of a new real-time communication service. It provides for efficient predictable and scalable communication between information producers and consumers. The CReMeS architecture is based on MidART's Real-Time Channel-based Reflective Memory (RT-CRM) abstraction. This architecture supports the separation of QoS specification between producer and consumer of data and employs a user-level scheduling scheme for communicating real-time tasks. These help us achieve end-to-end predictability and allows our service to scale. The CReMeS architecture provides a CORBA interface to applications and demands no changes to the ORB layer and the language mapping layer. Thus it can run on non real-time Off-The-Shelf ORBs enables applications on these ORBs to have scalable and end-to-end predictable asynchronous communication facility. In addition an application designer can select whether to use an out-of-band channel or the ORB GIOP/IIOP for data communication. This permits a trade-off between performance predictability and reliability. Experimental results demonstrate that our architecture can achieve better performance and predictability than a real-time implementation of the CORBA Even Service when the out-of-band channel is employed for data communication it delivers better predictability with comparable performance when the ORB GIOP/IIOP is used.

• Journal of Communications and Networks
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• v.9 no.4
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• pp.457-465
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• 2007

Native information provider(IP) anycast suffers from routing scalability issues and the lack of stateful communication support. For this reason, we propose architecture for scalable and transparent anycast services(ASTAS), a proxy-based architecture that provides support for stateful anycast communications, while retaining the transparency offered by native anycast. Dynamic resource assignment for each initiated session guarantees that a connection is established with the most suitable target server, based on network and server conditions. Traffic engineering in the overlay can be realized in an effective way due to the dissemination of aggregated state information in the anycast overlay. To minimize the total deployment cost for ASTAS architectures, we propose optimized proxy placement and path finding heuristics based on look-ahead information gathered in network nodes. Contrary to a regular integer linear program(ILP) formulation, these heuristics allow to optimize proxy placement in large networks. A use case on a European reference network illustrates that lower proxy costs enable proxy deployment closer to the end-users, resulting in a reduced network load.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.1
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• pp.379-394
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• 2012

The ever-increasing demand for H.264 scalable video coding (H.264/SVC) distribution motivates researchers to devise ways to enhance the quality of video delivered on the Internet. Furthermore, researchers and practitioners in general depend on computer simulators to analyze or evaluate their designed network architecture or proposed protocols. Therefore, a complete toolset, which is called myEvalSVC, for evaluating the delivered quality of H.264/SVC transmissions in a simulated environment is proposed to help the network and video coding research communities. The toolset is based on the H.264 Scalable Video coding streaming Evaluation Framework (SVEF) and extended to connect to the NS2 simulator. With this combination, people who work on video coding can simulate the effects of a more realistic network on video sequences resulting from their coding schemes, while people who work on network technology can evaluate the impact of real video streams on the proposed network architecture or protocols. To demonstrate the usefulness of the proposed new toolset, examples of H.264/SVC transmissions over 802.11 and 802.11e are provided.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.10 no.2
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• pp.97-102
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• 2010

In this paper, an area-efficient FFT processor is proposed for IEEE 802.16e mobile WiMax systems. The proposed scalable FFT processor can support the variable length of 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput. The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate-level circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 16% and 27%, respectively, compared with those of the 4-channel radix-2 MDC (R2MDC) FFT processor.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.12
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• pp.87-95
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• 2009

In this paper, an area-efficient FFT processor is proposed for MIMO-OFDM based SDR systems. The proposed scalable FFT processor can support the variable length of 64, 128, 512, 1024 and 2048. By reducing the required number of non-trivial multipliers with mixed-radix (MR) and multi-path delay commutator (MDC) architecture, the complexity of the proposed FFT processor is dramatically decreased without sacrificing system throughput The proposed FFT processor was designed in hardware description language (HDL) and synthesized to gate4eve1 circuits using 0.18um CMOS standard cell library. With the proposed architecture, the gate count for the processor is 46K and the size of memory is 64Kbits, which are reduced by 59% and 39%, respectively, compared with those of the 4-channel radix-2 single-path delay feedback (R2SDF) FFT processor. Also, compared with 4-channel radix-2 MDC (R2MDC) FFT processor, it is confirmed that the gate count and memory size are reduced by 16.4% and 26.8, respectively.

• Proceedings of the Korean Information Science Society Conference
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• 2004.04a
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• pp.382-384
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• 2004

최근 인터넷의 발달과 함께 인터넷 상에서의 데이터 보안에 대한 요구가 매우 증가되고 있다. 그래서 공개키 또는 비밀키 알고리즘을 사용하여 데이터 보안을 해결하고 있다. 대부분의 공개키 알고리즘은 모듈러 연산들을 기반으로 살고 있으며 이 중 복잡도가 가장 높은 모듈러 멱승 연산은 모듈러 곱셈 연산을 반복 수행하여 계산된다. 그래서 모듈러 곱셈연산을 효율적으로 계산하기 위한 많은 방법들이 제안되어 왔으며 하드웨어 구현 시 속도와 효율성 문제로 몽고메리 곱셈기에 대한 연구가 주목을 받아 왔다. 현재 몽고메리 곱셈 알고리즘을 이용한 곱셈기는 대부분이 성능과 면적만을 고려한 구조로 보안성 향상을 위해 입력 데이터의 비트수 증가 시 곱셈기의 구조 변경이 요구된다. 따라서 본 논문에서는 비트수 길이가 변하더라도 곱셈기 구조는 변함이 없는 GF(p)상에서의 Scalable한 몽고메리 곱셈기 구조를 제안한다. Sealable한 곱셈기의 구조는 FPGA와 같이 메모리를 포함하는 하드웨어 플랫폼에 적합하다. 제안된 구조는 Xilinx FPGA를 이용하여 하드웨어로 구현하며 ModelSim Tool을 통해 기능 및 타이밍 시뮬레이션을 수행한다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.177-183
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• 2015

A high speed VLSI digital Winner-Take-All (WTA) circuit called simultaneous digital WTA (SDWTA) circuit is presented in this paper. A minimized comparison-cell (w-cell) is developed to reduce the size and to achieve high-speed. The w-cell which is suitable for VLSI implementation consists of only four transistors. With a minimized comparison-cell structure SDWTA can compare thousands of data simultaneously. SDWTA is scalable with O(mlog n) time-complexity for n of m-bit data. According to simulations, it takes 16.5 ns with $1.2V-0.13{\mu}m$ process technology in finding a winner among 1024 of 16-bit data.

• ETRI Journal
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• v.26 no.1
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• pp.27-37
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• 2004

The architecture in a differentiated services (DiffServ) network is based on a simple model that applies a per-class service in the core node of the network. However, because the network behavior is simple, the network structure and provisioning is complicated. If a service provider wants dynamic provisioning or a better bandwidth guarantee, the differentiated services network must use a signaling protocol with QoS parameters or an admission control method. Unfortunately, these methods increase the complexity. To overcome the problems with complexity, we investigated scalable dynamic provisioning for admission control in DiffServ networks. We propose a new scalable $qDPM^2$ mechanism based on a centralized bandwidth broker and distributed measurement-based admission control and movable boundary bandwidth management to support heterogeneous QoS requirements in DiffServ networks.

• ETRI Journal
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• v.44 no.6
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• pp.915-924
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• 2022

In this paper, we present a two-stage scalable channel estimator (TSCE), a deep learning (DL)-based scalable, and robust channel estimator for wireless cellular networks, which is made up of two DL networks to efficiently support different resource allocation sizes and reference signal configurations. Both networks use the transformer, one of cutting-edge neural network architecture, as a backbone for accurate estimation. For computation-efficient global feature extractions, we propose using window and window averaging-based self-attentions. Our results show that TSCE learns wireless propagation channels correctly and outperforms both traditional estimators and baseline DL-based estimators. Additionally, scalability and robustness evaluations are performed, revealing that TSCE is more robust in various environments than the baseline DL-based estimators.