• Proceedings of the KIEE Conference
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• 대한전기학회 1996년도 하계학술대회 논문집 C
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• pp.1971-1973
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• 1996

In this paper various types of gyroscope fabricated by micromachining technologies were reviewed. Four common types of gyroscope reported in the past few years are beam, tuning fork, gimbal, and vibrating shell structure made by surface micromachining using sacrificial layer, bulk micromachining using RIE, or electroplating method. In the study of these new gyroscopes, the fabrication methods, advantages and disadvantages of each structure were examined as well as the direction of development in the future.

• Proceedings of the KIEE Conference
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• 대한전기학회 1994년도 추계학술대회 논문집 학회본부
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• pp.422-424
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• 1994

A comb drive electrostatic micro gripper was designed and fabricated. We designed it analytically using electrostatic force and cantilever deflection equation. In fabrication, we used LIGA-like technology consisted of Ni electroplating through polyimide patterned by $O_2$ Plasma RIE and Al sacrificial layer. This micro gripper was designed to handle an optical fiber which is $125{\mu}m$ in diameter.

• Korean Chemical Engineering Research
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• 제57권3호
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• pp.392-399
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• 2019

A highly transparent interfacial layer (HTIL) to enhance the performance of dye-sensitized solar cells (DSSCs) was prepared via a polymer-assisted (PA) approach. Poly(vinyl chloride)-graft-poly(oxyethylene methacrylate) (PVC-g-POEM) was synthesized via atom-transfer radical polymerization (ATRP) and was used as a sacrificial template. The PVC-g-POEM graft copolymer induced partial coordination of a hydrophilic titanium isopropoxide (TTIP) sol-gel solution with the POEM domain, resulting in microphase separation, and in turn, the generation of mesopores upon calcination. These phenomena were confirmed using Fourier-transform infrared (FT-IR) spectroscopy, UV-visible light transmittance spectroscopy, scanning electron microscopy (SEM), and X-ray diffraction (XRD) analysis. The DSSCs incorporating HTIL60/20 (consisting of a top layer with a pore size of 60 nm and a bottom layer with a pore size of 20 nm) exhibited the best overall conversion efficiency (6.36%) among the tested samples, which was 25.9% higher than that of a conventional blocking layer (BL). DSSC was further characterized using the Nyquist plot and incident-photon to electron conversion efficiency (IPCE) spectra.

• Proceedings of the Materials Research Society of Korea Conference
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• 한국재료학회 2010년도 춘계학술발표대회
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• pp.27.2-27.2
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• 2010

In recent years, there is a strong requirement of low cost, stable microelectro mechanical systems (MEMS) for resonators, microswitches and sensors. Most of these devices consist of freely suspended microcantilevers, which are usually made by the etching of some sacrificial materials. Herein, we have attempted to use Si nanowires, inherited from the parent Si wafer, as a sacrificial material due to its porosity, low cost and ease of fabrication. Prior to the fabrication of the Si nanowires silver nanoparticles were continuously formed on the surface of Si wafer. Vertically aligned Si nanowires were fabricated from the parent Si wafers by aqueous chemical route at $50^{\circ}C$. Afterwards, the morphological and structural characteristics of the Si nanowires were investigated. The morphology of nanowires was strongly modulated by the resistivity of the parent wafer. The 3-step etching of nanowires in diluted KOH solution was carried out at room temperature in order to control the fast etching. A layer of $Si_3N_4$ (300 nm) was used for the selective fabrication of nanowires. Finally, a freely suspended bridge of zinc oxide (ZnO) was fabricated after the removal of nanowires from the parent wafer. At present, we believe that this technique may provide a platform for the inexpensive fabrication of futuristic MEMS.

• Journal of Sensor Science and Technology
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• 제7권1호
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• pp.73-82
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• 1998

In silicon surface micro-machining, the newly developed GPE(gas-phase etching) process was verified as a very effective method for the release of highly compliant micro-structures. The developed GPE system with anhydrous HF gas and $CH_{3}OH$ vapor was characterized and the selective etching properties of sacrificial layers to release silicon micro-structures were discussed. P-doped polysilicon and SOI(silicon on insulator) substrate were used as a structural layer and TEOS(tetraethyorthdsilicate) oxide, thermal oxide and LTO(low temperature oxide) as a sacrificial layer. Compared with conventional wet-release, we successfully fabricated micro-structures with virtually no process-induced striction and residual product.

• Proceedings of the KIEE Conference
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• 대한전기학회 1998년도 하계학술대회 논문집 G
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• pp.2536-2538
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• 1998

This paper investigates the residual stress of tetraethoxysilane (TEOS) and 7wt% phosphosilicate glass (PSG), which are commonly used as a sacrificial layer or etch mask in the fabrication of microelectromechanical systems (MEMS). In order to measure residual stress, $2{\mu}m$ thick TEOS and PSG stress measurement structures are fabricated. Polysilicon is used as the sacrificial layer. First the residual stress of an as-deposited 7wt% PSG flim and TEOS film are measured to be-0.3115% and -0.435%, respectively, which are quite large. These films are annealed from $500^{\circ}C$ to $800^{\circ}C$. Annealing has the effects of reducing residual stress. In the case of the 7wt% PSG film, the residual stress becomes +0.00715% after annealing at $625^{\circ}C$ for 150 minutes. In the case of TEOS film, the residual stress reduces to -0.2134% after same condition. Incidentally, this condition is the same condition for depositing a $2{\mu}m$ thick polysilicon at $625^{\circ}C$ at our low pressure chemical vapor deposition (LPCVD) furnace.

• Proceedings of the KIEE Conference
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• 대한전기학회 1995년도 하계학술대회 논문집 C
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• pp.1419-1421
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• 1995

Nickel micro-structures are fabricated by electroless plating which shows better uniformity. Positive resist AZ4562 of 7 um thickness is patterned with minimum width of 2 um on poly-silicon as for sacrificial layer. The growth rate of Ni electroless plating is 10um/h both for the seed layer of Pt and TiW. TiW is found to be more practical than Pt, since it is very difficult to remove Pt with negligible damage to Ni structures.

• Journal of the Korean Institute of Telematics and Electronics D
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• 제35D권9호
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• pp.48-53
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• 1998

We have fabricated electrostatic lens with novel structure by mixing surface- and bulk-micromachining technology. Polysilicon was used for both the structure and sacrificial layer, and the structure layer was passivated with thermal oxide in order not to be attacked during the silicon wet etching. Compared with conventional electrostatic lens used in microcolumn, this device has the advantages in ; 1) hole alignment, throughput, reliability, damage of lens, 2) the possibility of arrayed lithography through the integration of microcolumn.

• Journal of Sensor Science and Technology
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• 제15권5호
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• pp.357-361
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• 2006

This paper reports a new technology to implement complex PDMS microchannels, which are simply constructed using three-dimensional photoresist structures as mold for PDMS replica process. The process utilizes LOR resist as a sacrificial layer to levitate the structural photoresist and multi-step exposure to control the thicknesses of photoresist structures. Various shapes of photoresist structures were successfully fabricated. Using the PDMS replica method, the three-dimensional photoresist structures are demonstrated to be applicable for implementing complex microchannels in PDMS. In addition, more complex multilevel microchannels are constructed by bonding two PDMS layers with just single PDMS alignment.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• 제17권2호
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• pp.212-216
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• 2004

In this paper, we have fabricated a triode field emitter using carbon nanotubes (CNTs) directly grown by thermal chemical vapor deposition(CVD) method as an electron omission source. Vertically aligned CNTs have been grown in the center of the gate hole, to the size of 1.5 ${\mu}{\textrm}{m}$ in diameter, with help of a sacrificial layer of a type generally used in metal tip process. By the method of tilling the substrate, we made CNTs emitters both with and without SiO$_2$layer, a sidewall protector, deposited on sidewall of gate. After that we researched the electrical characteristics about two types of emitters. In effect, a sidewall protector can enhance the electrical characteristics by suppressing the problem of short circuits between the gate and the CNTs. The leakage current of an emitter with a sidewall protector is approximately sevenfold lower than that of an emitter without it at a gate voltage of 100 V.