• ETRI Journal
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• v.26 no.6
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• pp.657-660
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• 2004

We propose a fine phase tuner and a rounding processor for a numerically controlled oscillator (NCO), yielding a reduced phase error in generating a digital sine waveform. By using the fine phase tuner presented in this paper, when the ratio of the desired sine wave frequency to the clock frequency is expressed as a fraction, an accurate adjustment in representing the fractional value can be achieved with simple hardware. In addition, the proposed rounding processor reduces the effects of phase truncation on the output spectrum. Logic simulation results of the NCO using these techniques show that the noise spectrum and mean square error (MSE) for eight output bits of a 3.125 MHz sine waveform are reduced by 8.68 dB and 5.5 dB, respectively, compared to those of the truncation method, and 2.38 dB and 0.83 dB, respectively, compared to those of Paul's scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11A
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• pp.1271-1277
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• 2004

We propose a foe phase tuner and a rounding processor for a numerically controlled oscillator (NCO), yielding a reduced phase error in generating a digital sine waveform. By using the fine Phase tuner Presented in this paper, when the ratio of the desired sine wave frequency to the clock frequency is expressed as a fraction, an accurate adjustment in representing the fractional value can be achieved with simple hardware. In addition, the proposed rounding processor reduces the effects of phase truncation on the output spectrum. Logic simulation results of the NCO for multi-carrier channel separation in cdma2000 3X multi-carrier receive system using these techniques show that the noise spectrum and mean square error (MSE) are reduced by 8.68 dB and 5.5 dB, respectively compared to those of truncation method and 2.38 dB and 0.83 dB, respectively, compared to those of Paul's scheme.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1433-1443
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• 1993

DCT(Discrete Cosine Transform) / IDCT(Inverse DCT) is widely used in various image compression and decompression systems as well as in DSP(Digital Signal Processing) applications. Since DCT/ IDCT is one of the most complicated part of the compression system, the performance of the system can be greatly enchanced by improving the speed of DCT/IDCT operation. In this thesis, we designed a DCT/IDCT core processor using module generator technique. By utilizing the partial sum and DA(Distributed Arithmetic) techniques, the DCT/ IDCT core processor is designed within small area. It is also designed to perform the IDCT(Inverse DCT) operation with little additional circuitry. The pipeline structure of the core processor enables the high performance, and the high accuracy of the DCT/IDCT operation is obtained by having fewer rounding stages. The proposed design is independent of design rules, and the number of the input bits and the accuracy of the internal calculation coa be easily adjusted due to the module generator technique. The accuracy of the processor satisfies the specifications in CCITT recommendation H, 261.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.4
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• pp.129-134
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• 2017

In the present society, our current technology associated with bakery industry has been improved as much as technical development can get abreast of the Western one where the bread has originated and has been awarded and ranked in the highest level of many bakery or pastry competitions. In these trends, many people are running for high value added business such as bakery industry and bakery $caf{\acute{e}}$, etc. with big interest. However, high labor cost of technician and difficulties in human resource management become obstruction factors in the growth of the bakery industries. Therefore, in this paper, the designed system for both dividing and rounding dough quickly and exactly at the same time was studied. The main function of this system is to divide the original dough into 3 tracks and then, to place 4 doughs in the inner track, 12 doughs in the mid track, 20 doughs in the outer track, totally 36 doughs in a routine. It takes much energy because 36 doughs can be completed in a routine. Therefore, this system uses hydraulic pressure and a 0.75Kw induction motor is used for dough rounding. This system can make primarily fermented dough into 36 divided doughs very quickly and exactly on a guide panel at the desired weight by dividing it within 1-9 seconds and by rounding each within 1-9 seconds. This system is very effective in bakery industry to minimize labor cost and it is expected to supply more hygienic products to the customers.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.711-714
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• 2005

We propose floating point arithmetic units for geometry operation of mobile 3D graphic processor. The proposed arithmetic units conform to the single precision format of IEEE standard 754-1985 that is a standard of floating point arithmetic. The rounding algorithm applies the nearest toward zero form. The proposed adder/subtraction unit and multiplier have one clock cycle latency, and the inversion unit has three clock cycle latency. We estimate the required numbers of arithmetic operation for Viewing transformation. The first stage of geometry operation is composed with translation, rotation and scaling operation. The translation operation requires three addition and the rotation operation needs three addition and six multiplication. The scaling operation requires three multiplication. The viewing transformation is performed in 15 clock cycles. If the adder and the multiplier have their own in/out ports, the viewing transformation can be done in 9 clock cycles. The error margin of proposed arithmetic units is smaller than $10^{-5}$ that is the request in the OpenGL standard. The proposed arithmetic units carry out operations in 100MHz clock frequency.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.1 no.1
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• pp.75-79
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• 1983

現代 컴퓨터의 연산장치(Arithmetic unit)의 design을 하는데 있어서 가장 중요하게 요구점점되는 點은 계산의 속도(Computational speed)와 計算의 정확성 (Computational accuracy)이라고 보겠다. 여기서는 정보처리기(Information processor)로서 또는 非數理的인 연산(Non-numeric operation)을 위한 도구로서 보다는 數理的 연산(Arithmetic)을 수행하는 도구로서의 컴퓨터 연산에 限해서만 論하고자 한다. 대개의 경우 기계를 고안하는 사람들은 계사의 속도에 對해서는 특별한 관심을 갖고 그러한 목적에 맞는 기계를 만들어 낼려고 하지만 數値의 정 확성(Numerical accuracy)에 對해서ㅡ 등한시했던 경우가 많았다고 보겠다. 그러 나 이 두 條件 즉 빠른 속도 틀림없는 정확성을 同時에 충족 시키고자 하는 것이 기계 고안자들의 理想 목포가 되는 것은 사시링다. 여기에 수반도는 문제는 제작 비를 고려하지 않을 수 없다는 것이다. 정화하고 빠른 operation을 할 수 있는 기 계는 너무 비싼 제작비가 들기 때문에 사용목적에 적절하게 두 문제를 절충하여 고려하는 것이 일반적이라 하겠다. 初期의 컴퓨터는 한 Word(Computer Word)로 서 36개의 bit를 사용한 것이 많았다고 본다. 그러나 1961년 4月 Tennessee에서 Oak Riage National Laboratory와 The Society for Industril and Applied Mathematics 후원하에 일주일에 걸친 국제회의가 열렸었는데 거기 모인 거의 모 든 學者들이 앞으로의 과학 연구용 컴퓨터(Scientific Computer)의 한 Word의 길 이는 적어도 48bit 이상으로 증가시켜야 된다는데 의견을 모았었다고 한다. 이제 rounding error의 성향(begavior)을 알아보기 위한 간단한 例를 들어 봄으로써 이 글을 쓰는 동기으 일면을 대신하고자 한다.

• Management & Information Systems Review
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• v.4
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• pp.257-284
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• 2000

According as the drivers increase who have their cars, the comprehensive studies on the automobile for the traffic safety have been raised as the important problems. Visual Recognition System for radio-controled driving is a part of the sensor processor of Unmanned Autonomous Vehicle System. When a driver drives his car on an unknown highway or general road, it produces a model from the successively inputted road traffic information. The suggested Recognition System of the Road Traffic Safety Information Board is to recognize and distinguish automatically a Road Traffic Safety Information Board as one of road traffic information. The whole processes of Recognition System of the Road Traffic Safety Information Board suggested in this study are as follows. We took the photographs of Road Traffic Safety Information Board with a digital camera in order to get an image and normalize bitmap image file with a size of $200{\times}200$ byte with Photo Shop 5.0. The existing True Color is made up the color data of sixteen million kinds. We changed it with 256 Color, because it has large capacity, and spend much time on calculating. We have practiced works of 30 times with erosion and dilation algorithm to remove unnecessary images. We drawing out original image with the Region Splitting Technique as a kind of segmentation. We made three kinds of grouping(Attention Information Board, Prohibit Information Board, and Introduction Information Board) by RYB( Red, Yellow, Blue) color segmentation. We minimized the image size of board, direction, and the influence of rounding. We also minimized the Influence according to position. and the brightness of light and darkness with Eigen Vector and Eigen Value. The data sampling this feature value appeared after building the learning Code Book Database. The suggested Recognition System of the Road Traffic Safety Information Board firstly distinguished three kinds of groups in the database of learning Code Book, and suggested in order to recognize after comparing and judging the board want to recognize within the same group with Nearest Neighborhood Decision Making.