• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.4
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• pp.57-66
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• 2004

This paper proposes the design of a 2,048-bit RSA based on RNS(residue number systems) Montgomery modular multiplier As the systems that RNS processes a fast parallel modular multiplication for a large word partitioned into small words, we introduce Montgomery reduction method(MRM)［1］based on Wallace tree modular multiplier and 33 RNS bases with 64-bit size for RNS Montgomery modular multiplication in this paper. Also, for fast RNS modular multiplication, a modified method based on Chinese remainder theorem(CRT)［2］ is presented. We have verified 2,048-bit RSA based on RNS using Samsung 0.35${\mu}{\textrm}{m}$ technology and the 2,048-bit RSA is performed in 2.54㎳ at 100MHz.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.9
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• pp.454-460
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• 2003

In this paper, we present a novel method of parallelization of the modular multiplication algorithm to improve time and space complexity on RNS (Residue Number System). The parallel algorithm executes modular reduction using new table lookup based reduction method. MRS (Mixed Radix number System) is used because algebraic comparison is difficult in RNS which has a non-weighted number representation. Conversion from residue number system to certain MRS is relatively fast in residue computer. Therefore magnitude comparison is easily Performed on MRS. By the analysis of the algorithm, it is known that it requires only 1/2 table size than previous approach. And it requires 0(ι) arithmetic operations using 2ㅣ processors.

• ETRI Journal
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• v.38 no.2
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• pp.326-336
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• 2016

We propose and describe new error control algorithms for redundant residue number systems (RRNSs) and residue number system product codes. These algorithms employ search techniques for obtaining error values from within a set of values (that contains all possible error values). For a given RRNS, the error control algorithms have a computational complexity of $t{\cdot}O(log_2\;n+log_2\;{\bar{m}})$ comparison operations, where t denotes the error correcting capability, n denotes the number of moduli, and ${\bar{m}}$ denotes the geometric average of moduli. These algorithms avoid most modular operations. We describe a refinement to the proposed algorithms that further avoids the modular operation required in their respective first steps, with an increase of ${\lceil}log_2\;n{\rceil}$ to their computational complexity. The new algorithms provide significant computational advantages over existing methods.

• Journal of the Korean Institute of Intelligent Systems
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• v.15 no.2
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• pp.224-229
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• 2005

Generally, genetic algorithm (GA) has too much time and space complexity when it is running in the typical processor. Therefore, we are forced to use the high-performance and expensive processor by this reason. It also works as a barrier to implement real device, such a small mobile robot, which is required only simple rules. To solve this problem, this paper presents and proposes enhanced processor-architecture for the faster GA processing. A typical processor architecture can be enhanced and specialized by two approaches: one is a sorting network, the other is a residue number system (RNS). A sorting network can improve the time complexity of which needs to compare the populations' fitness. An RNS can reduce the magnitude of the largest bit that dictates the speed of arithmetic operation. Consequently, it can make the total logic size smaller and innovate arithmetic operation speed faster.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 2004.10a
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• pp.169-172
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• 2004

유전 알고리듬은 NP-Hard 문제의 해결이나, 함수 최적화, 복잡한 제어기의 파라미터 값 추적 등, 광범위한 분야에 걸쳐 이용되고 있다 일반적인 유전 알고리듬은 적합도 함수를 통해 해들의 품질을 결정하고, 해들의 품질에 따라 선택 연산을 거쳐, 교차나 돌연변이를 통해 우수한 품질의 해를 찾는 과정을 가진다 현재 이 과정은 대부분 소프트웨어적으로 구현되어 범용 프로세서를 통해 수행된다. 그러나 높은 소프트웨어 의존성은 해집단의 크기가 커질수록 교차/변이 연산과 해들의 품질비교에 수행되는 시간을 크게 증가시키는 약점이 있다. 따라서 본 논문에서는 순위 기반 선택과 일점 교차(one-point crossover)를 사용한다는 제약하에, 해들의 순위를 정렬 네트워크를 통해 결정하고 해들을 Residue Number System(RNS)로 표현하여 하드웨어적으로 교차연산을 처리하는 프로세서 구조를 제안한다 이러한 접근을 통해 해들의 품질비교에 걸리는 시간을 크게 줄이고 교차/변이 연산의 효율을 높일 수 있다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.3
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• pp.340-344
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• 1986

This paper shows that we can design a vector-coordinate rotation processor and obtain the approximate evaluations of sine and cosine based upon the use of residue number systems. The algorithm results in the considerable improvement of the computation speed when compared to CORDIC algorithm. The results from computer simulation show that the mean error of sine and cosine is 0.0025 and the mean error of coordinate rotation arithmatic is 0.65. Also, the proposed processor has the efficiency for the design and fabrication of integrated circuit, because it consists of the array of idecntially structured look-up tables.

• Journal of KIISE:Computer Systems and Theory
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• v.30 no.12
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• pp.749-755
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• 2003

Digital signal processing hardware based in RNS is currently considered as an important method for high speed and low cost hardware realization. This research designs and implements the method for conversion from a specific residue number system with moduli of the from $(2^k-1, 2^k, 2^k+1)$ to a weighted number system. Then, it simulates the implementation using a overlapped multiple-bit scanning method in the process of CRT conversion. In conclusion, the simulation shows that the CRT method which is adopted in this research, performs arithmetic operations faster than the traditional approaches, due to advantages of parallel processing and carry-free arithmetic operation.