• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.6
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• pp.1080-1086
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• 1987

SLAGEN, a system for symbolic cell layout based on artificial intelligence approach, takes as input a transistor connection description of CMOS standard cells and environment information, and outputs a symbolic layout description. SLAGEN performas transistor grouping by a heuristic search method, in order to minimize the number of separations, and then performs group reordering and transistor reordering with an eye toward minimizing routing. Next, SLAGEN creates a rough initial routing in order to guarantee functionality and correctness, and then improve the initial routing by a rule-based approach.

• Communications of the Korean Institute of Information Scientists and Engineers
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• v.5 no.2
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• pp.85-89
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• 1987

The large sparse matrix problems arise in many applications areas, such as structural analysis, network analysis. In dealing with such sparse systems proper preprogramming techniques such as permuting rows and columns simultaneously, will be needed in order to reduce the number of arithmetic operations and storage spaces.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.12 no.6
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• pp.215-221
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• 2012

To address the bottleneck problem in data center networks, there have been several proposals for network architectures providing high path-diversity. In devising new schemes to utilize multiple paths, one must consider the effects on TCP performance because packet reordering can make TCP perform poorly. Therefore most schemes prevent packet reordering by sending packets through one of multiple available paths. In this study we show that packet reordering does not occur severely enough to have a significant impact on TCP performance when scattering packets through all available paths between a pair of hosts in Fat-Tree. Simulation results imply that it is possible to find a low-cost solution to the TCP performance problem for Fat-Tree-like topologies.

• Journal of Broadcast Engineering
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• v.2 no.2
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• pp.94-104
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• 1997

This paper presents a new vertex-based binary shape coding scheme using one-dimensional vertex selection/encoding and vertex reordering. In compared with the conventional object-adaptive vertex encoding(OA VEL the extracted vertices are, firstly, classified into one-dimensional(lD) vertices and two-dimensional (2D) vertices in the proposed method. For lD vertices, new coding method proposed in this paper is performed. For 2D vertices, the vertex reordering and OA VE are carried out. Experimental results show that the proposed vertex-based coding scheme red.uces coding bits up to 12 % compared with the conventional one and its coding gain depends on the characteristics of contour.

• ETRI Journal
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• v.37 no.1
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• pp.147-156
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• 2015

A typical solid-state drive contains several independent channels that can be operated in parallel. To exploit this channel-level parallelism, a variety of works proposed to split consecutive write sequences into small segments and schedule them to different channels. This scheme exploits the parallelism but breaks the spatial locality of write traffic; thus, it is able to significantly degrade the efficiency of garbage collection. This paper proposes a channel-aware write reordering (CAWR) mechanism to schedule write requests to different channels more intelligently. The novel mechanism encapsulates correlated pages into a cluster beforehand. All pages belonging to a cluster are scheduled to the same channels to exploit spatial locality, while different clusters are scheduled to different channels to exploit the parallelism. As CAWR covers both garbage collection and I/O performance, it outperforms existing schemes significantly. Trace-driven simulation results demonstrate that the CAWR mechanism reduces the average response time by 26% on average and decreases the valid page copies by 10% on average, while achieving a similar hit ratio to that of existing mechanisms.

• The Journal of the Korea Contents Association
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• v.5 no.1
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• pp.229-236
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• 2005

Testing time and power consumption during testing System-On-a-Chip (SOC) are becoming increasingly important as the IP core increases in a SOC. We present a new algorithm to reduce the scan-in power and test data volume using the modified scan latch reordering. We apply scan latch reordering technique for minimizing the hamming distance in scan vectors. Also, during scan latch reordering, the don't care inputs in scan vectors are assigned for low power and high compression. Experimental results for ISCAS 89 benchmark circuits show that reduced test data and low power scan testing can be achieved in all cases.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.11 no.6
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• pp.81-86
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• 2011

In one of the most impacting schemes proposed to address the TCP throughput problem over network coding, the network coding layer sends an acknowledgement if an innovative linear combination is received, even when a new packet is not decoded. Although this scheme is very effective, its implementation requires a limit on the coding window size. This limitation causes low TCP throughput in the presence of packet reordering. We argue that a TCP variant detecting a packet loss relying only on timers is effective in dealing with the packet reordering problem in network coding environments as well. Also we propose a new network coding layer to support such a TCP variant. Simulation results for a 2-path environment show that our proposed scheme improves TCP throughput by 19%.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.10B
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• pp.638-643
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• 2007

Interconnecting wireless local area networks (WLANs) with third generation (3G) cellular networks has become an issue of great interest. However, a Vertical Handover (VHO) causes an abrupt change in link bandwidth. Due to such a change, TCP triggers unnecessary fast retransmission during a Downward VHO (DVHO) from a cellular network to a WLAN, causing throughput degradation. Thus, we propose a new reordering mechanism for DVHO that suppresses unnecessary retransmission due to the spurious duplicate acknowledgments. We analytically investigate the throughput of TCP in the literature and our proposed scheme. Through the numerical and simulation results, it is shown that our proposed TCP achieves better performance in terms of throughput, compared with Nodupack with SACK.

• The KIPS Transactions:PartB
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• v.9B no.5
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• pp.609-614
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• 2002

Watermarking is embedding a digital signal called as watermark into images to claim the ownership. In this paper, a new digital watermarking algorithm based on DCT (Discrete Cosine Transform) which enhances invisibility and robustness is proposed to improve contentional digital watermarking method using DCT. In the proposed method, it is possible to enhance invisibility and robustness using watermark reordering in which the relative significance of original DCT coefficients can be preserved in watermarked DCT coefficients, and the distortions of original DCT coefficients can be minimized. The experimental results show that the proposed method improves invisibility approximately 9～12[dB] and is more robust to various attacks than the conventional method.

• Journal of Computing Science and Engineering
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• v.11 no.2
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• pp.58-68
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• 2017

While graphics processing units (GPUs) can be used to improve the performance of real-time embedded applications that require high throughput, it is challenging to estimate the worst-case execution time (WCET) of GPU programs, because modern GPUs are designed for improving the average-case performance rather than time predictability. In this paper, a reordering framework is proposed to regulate the access to the GPU data cache, which helps to improve the accuracy of the estimation of GPU L1 data cache miss rate with low performance overhead. Also, with the improved cache miss rate estimation, tighter WCET estimations can be achieved for GPU programs.