• Proceedings of the Korean Society of Surveying, Geodesy, Photogrammetry, and Cartography Conference
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• 2006.04a
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• pp.235-241
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• 2006

The demand of 3D terrain mapping techniques is increasing in many application fields such as CNS(Car Navigation System), web service system, DMB(Digital Multimedia Broadcasting) systems and etc To construct a 3D terrain map, it is a pre-requite step that register data collected from different surveying sources. This Paper Present the methodology to register airborne photo, LIDAR data, and digital map, which are major data sources to create a 3D terrain mao. For this purpose, we developed the generally applicable algorithm that uses linear features to register airborne photos and digital maps to LIDAR data. The algorithm explicitly formulates step-by-step methodologies to establish observation equations for transformation. The results clearly demonstrate the proposed algorithm is appropriate to register these data sources.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1424-1425
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• 2011

비절질 IGZO TFT를 제작하여 양의 DC 및 AC에 대한 bias stability를 측정하였다. 소자특성이 상당부분 양의 방향으로 움직여 전류가 감소하였다. 따라서 기존의 Shift-Register는 양의 스트레스 전압을 지속적으로 받기 때문에 회로가 제대로 동작하지 않을 수 있다. 따라서 우리는 양의 스트레스 전압을 받지않는 새로운 Shift-register를 고안하고 SPICE 시뮬레이션을 통하여 안정한 출력을 확인하였다.

• Proceedings of the KIEE Conference
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• 2006.07d
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• pp.1809-1810
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• 2006

Existing a high-speed printer register controller have used a foreign country goods of the high price. It established the plan to be and progressed to progress research. It find out about former time's a register control system's action. and determined the processor to DSP. It studied the algorithm to consider various situations. It completed finally a simulator board of a register controller of the high capacity.

• JSTS:Journal of Semiconductor Technology and Science
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• v.9 no.3
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• pp.148-152
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• 2009

Recent CMOS technology scaling has seriously eroded the bit-line noise immunity of register files due to the consequent increase in active bit-line leakage currents. To restore its noise immunity while maintaining performance, we propose and evaluate a $256{\times}40$-bit register file incorporating dual-$V_t$ bit-lines with a boosted gate overdrive voltage in 65 nm bulk CMOS technology. Simulation results show that the proposed bootsrapping scheme lowers leakage current by a factor of 450 without its performance penalty.

• Korea journal of population studies
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• v.12 no.2
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• pp.56-68
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• 1989

The methodology in historical demography comprises the three core areas the family reconstitution method at the Institut National d' Ftudes Demographiques(I.N.E.D), the back projection at the Cambridge Group for the History of PopuJation and Social Struc-ture(HPSS). and the household-pattern analysis at the Cambridge Group and at the California Institute of Technology. The paper presents an outline of the family reconstitu-tion method and discusses the problems, both theoretical and methodological, arising from the problematic back projection vis-a-vis the usual inverse projection developed by Ronald D. Lee at Berkeley. Recent developments in the tield of the generalized inverse projection method designed 10 supplement the defects in the back projection and the inverse projection are presented. and for ease of explanation of the parish register data for the family reconstitution form (FRE). pre-modern Korean household register data are presented along with the parish register data of England and Wales that constitute the backbone of historical demography in pre-modern Europe. Possibilities of exploring the household pattern analysis method based on the Laslett-Hammel classification scheme for the mid-eighteenth-century Korean household register data are suggested.

• JSTS:Journal of Semiconductor Technology and Science
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• v.7 no.4
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• pp.229-234
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• 2007

In this paper, we present an efficient instruction set architecture using vector register file hardware to accelerate operation of general matrix-vector operations in DSP microprocessor. The technique enables in-situ row-access as well as column access to the register files. It can reduce the number of memory access significantly. The technique is especially useful for block-based video signal processing kernels such as FFT/IFFT, DCT/IDCT, and two-dimensional filtering. We have applied the new instruction set architecture to in-loop deblocking filter processing in H.264 decoder. Performance comparisons show that the required load/store operations for the in-loop deblocking filter can be reduced about 42%. The architecture would improve the processing speed, and code density in DSP microprocessor especially for video signal processing substantially.

• IEMEK Journal of Embedded Systems and Applications
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• v.7 no.1
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• pp.41-52
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• 2012

Recently, FlexRay was developed to replace controller area network (CAN) protocol in chassis networking systems, to remedy the shortage of transmission capacity and unsatisfactory real-time transmission delay of conventional CAN. FlexRay network systems require correct synchronization and complex scheduling parameters. However, because platform configuration register (PCR) setting and message scheduling is complex and bothersome task, FlexRay is more difficult to implement in applications than CAN protocol. To assist a network designer for implementing FlexRay cluster, this paper presents an analysis of FlexRay platform configuration register and automatic generation program of PCR. To demonstrate the feasibility of the automatic generation program, we evaluated its performance using experimental testbed.

• Journal of Information Display
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• v.12 no.1
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• pp.61-67
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• 2011

A single-clock-driven shift register and a two-stage buffer are proposed, using p-type, low-temperature polycrystalline silicon thin-film transistors. To eliminate the clock skew problems and to reduce the burden of the interface, only one clock signal was adopted to the shift register circuit, without additional reference voltages. A two-stage, p-type buffer was proposed to drive the gate line load and shows a full-swing output without threshold voltage loss. The shift register and buffer were designed for the 3.31" WVGA ($800{\times}480$) LCD panel, and the fabricated circuits were verified via simulations and measurements.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.3
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• pp.459-465
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• 1987

This paper describes the circuit and the layout of the shift register which can be used for a scanner of image sensor. P-well concentration and threshold voltage for proper iperation are calculated on the basso of the fixed process and the layout design. The calculation procedure of maximum operation frequency is also carried out. It is ascertained by SPICE simulation that the shift register produces the outputn pulse without threshold voltage loss up to 13MHz.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.11a
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• pp.23-24
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• 2008