• 자동차안전학회지
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• 제16권1호
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• pp.6-11
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• 2024

This paper presents a motion planning algorithm of autonomous racing vehicles for mimicking the characteristics of a human driver. Time optimal maneuver of a race car has been actively studied as a major research area over the past decades. Although the time optimization problem yields a single time series solution of minimum time maneuver inputs for the vehicle, human drivers achieve similar lap times while taking various racing lines and velocity profiles. In order to model the characteristics of a specific driver and reproduce the motion, a stochastic motion planning framework based on kernelized motion primitive is introduced. The proposed framework imitates the behavior of the generated reference motion, which is based on a small number of human demonstration laps along the racetrack using Gaussian mixture model and Gaussian mixture regression. The mean and covariance of the racing line and velocity profile mimicking the driver are obtained by accumulating the outputs tested at equidistantly sampled input points. The results confirmed that the obtained lateral and longitudinal motion simulates the driver's driving characteristics, which are feasible for actual vehicle test environments.

• 전자공학회논문지SC
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• 제39권2호
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• pp.132-139
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• 2002

본 논문은 전원전압 감지기와 소비전력이 적은 SRAM 쓰기 구동기에 대한 것이다. 전원전압 감지기는 전원전압이 기준전압보다 높을 때는 하이, 낮을 때는 로우를 발생한다. 쓰기 구동기는 쓰기 사이클에서 동작 전류를 줄이기 위해 가변 구동력을 가진 이중 크기 구조를 사용하였다. 전원전압 감지 결과에 따라 로우일 경우에는 두개의 구동기를 동작하게 하여 기존과 구동능력이 같고 하이일 경우에는 한개의 구동기만 동작하여 전류를 반으로 흘리도록 하여 저전력을 구현하였다. 0.6㎛ 3.3v/5v, CMOS 모델 파라메타를 가지고 모의 실험한 결과, 제안한 SRAM회로는 Vcc=3.3V에서 기존과 비교하여 전력소모를 22.6%, PDP(Power- delay-product)를 12.7% 감소한 결과를 보였다.

• Journal of information and communication convergence engineering
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• 제10권1호
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• 한국정보시스템학회지:정보시스템연구
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• 제15권3호
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• pp.107-129
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• 2006

The purpose of this study is to provide and validate an IT cost model hi which we link among cost center, cost object and flexible cost driver. in order to accomplish this purpose, this study utilizes ethnographic research methodology. At first we develop the cost model where the flexible cost driver is the distribution basis of overhead cost. For each cost driver, unit cost management model is also proposed. Then we employ the structured design methodology to validate the model. Based on the IT Cost requirements of a case company, the IT cost system was designed and developed for its test. The result shows the model we developed in this study is appropriate for managing IT resources and further, can be used as a reference model for calculating chargeback rates of other departments and IT budget of IT department.

• 산업기술연구
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• 제27권B호
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• pp.125-128
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• 2007

This paper presents Spectral-Domain optical measurement system using self-fabricated CCD sensor driver. The light source is a high brightness white LED and the detector is a 2048 array typed CCD image sensor. I have fabricated the CCD sensor driver to generate four pulse signals, which are the CCD-driving pulses. Using this Spectral Domain optical measurement system, the distance value between the reference mirror and the sample mirror can be obtained successfully.

• 정보기술과데이타베이스저널
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• 제7권1호
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• pp.42-53
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• 2000

The major goal of this research is to develop an optimal route search algorithm for an intelligent route guidance system, one sub-area of ITS. ITS stands for intelligent Transportation System. ITS offers a fundamental solution to various issues concerning transportation and it will eventually help comfortable and swift moves of drivers by receiving and transmitting information on humans, roads and automobiles. Genetic algorithm, and fuzzy logic are utilized in order to implement the proposed algorithm. Using genetic algorithm, the proposed algorithm searches shortest routes in terms of travel time in consideration of stochastic traffic volume, diverse turn constraints, etc. Then using fuzzy logic, it selects driver-preference optimal route among the candidate routes searched by GA, taking into account various driver's preferences such as difficulty degree of driving and surrounding scenery of road, etc. In order to evaluate this algorithm, a virtual road-traffic network DB with various road attributes is simulated, where the suggested algorithm promptly produces the best route for a driver with reference to his or her preferences.

• Journal of Advanced Marine Engineering and Technology
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• 제22권6호
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• pp.928-934
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• 1998

This paper describes a fully digitalized driver for BLDC motors which is realized by a single chip microprocessor. The speed change can be done by using the signal obtained from the position detecting sensor and adjusting the pulse width at the input channel of power module. In order to establish a speed control system a repetitive control method is adopted to track a periodic refer-ence change in the BLDC motor system. The experimental results show accurate reference track-ing performance under the given periodic reference in the repetitive controller design.

• 한국통신학회:학술대회논문집
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• 한국통신학회 2004년도 추계종합학술대회 논문 초록집
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• pp.229-229
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• 2004

• 조명전기설비학회논문지
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• 제21권10호
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• pp.1-12
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• 2007

본 실험에서는 운전자의 시인성을 측정하였다. 운전자의 시인성은 전압패턴에 따라 피험자의 장애물 인식 반응시간을 측정하여 분석하였고, 남녀 성별 간의 장애물 인식 반응시간의 차이를 분석하였다. 또한 전조등의 전압변동에 의한 밝기 비율에 따라서 피험자의 장애물 인식 반응속도를 분석하였고, 전압변동이 없을 때의 장애물 인식 반응시간을 기준으로 상대적인 장애물 인식 지연시간을 분석하였다.

• 한국정보통신설비학회:학술대회논문집
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• 한국정보통신설비학회 2005년도 하계학술대회
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• pp.159-165
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• 2005

The proposed optical transmitter is composed of FF(flip flop) , PLL (phase locked loop), reference clock generator, serializer and LD driver 10x250 Mb/s data arrays are translated to the 2.5 Gb/s data signal by serializer. In this case, 1 data bus is allocated usually as a reference clock for synchronization. In this proposed optical transmitter, 125 MHz reference clock is generated from 10x250 Mb/s data arrays by reference clock generator. From this method. absent of reference clock bus is available and more data transmission become possible. To achieve high speed operation, the serializer circuit is designed as two stacks. For 10:1 serialization, 10 clocks that have 1/10 lambda differences is essential, so the VCO (voltage controlled oscillator) composed of 10 delay buffers is designed. PLL is for runing at 250 MHz, and dual PFD(phase frequency detector) is adopted for fast locking time. The optical transmitter is designed by using 0.35 um CMOS technology.