• Journal of the Korean Society for Nondestructive Testing
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• v.19 no.5
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• pp.363-368
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• 1999

Ultrasonic pulse-echo methods measuring the transit time through specimens have been widely used in determination of ultrasonic velocity and thickness of specimens. Usually, to determine the velocity of the ultrasonic. the transit time of the ultrasonic pulse through specimen is measured by using the ultrasonic measuring equipment such as the oscilloscope including ultrasonic pulser/receiver and the thickness of the specimen is measured by using the length measuring instrument such as micrometer or vernier calipers etc., i. e. each parameter is measured by using each measuring method. In the case of the measuring the thickness of a specimen by using the ultrasonics. the ultrasonic equipments, which measure the thickness, such as the ultrasonic thickness gauge must be calibrated by using the reference block of which the ultrasonic velocity is known beforehand. In the present work, we proposed a new method for simultaneous measurement of ultrasonic velocity and thickness without reference blocks. Experimental results for several specimens show that proposed method have good agreements with those by traditional ultrasonic method.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.8
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• pp.2064-2071
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• 1998

A new digital clock level translator has been designed in order to produce a clock source of the internal logic circuits. The translator output has 50% duty ratio from small sinusoidal input such as TCXO which oscillates itself in poratable components. The circuit consists of positive and negative comparators, RS latch, charge pump, and reference vol- tage generator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator. It detects pulse width of the output waveform and feedbacks the control signal to the input com-parator reference, producing output waveform with valid 50% duty ratio of the digital signal level. The designed level translator can be used as a sampling clock source of ADC, PLL and the colck source of the clock synthesizer. The circuit wasdesigned in a 0.8.mu.m analog CMOS technology with double metal, double poly, and BSIM3 circuit simulation model. From our experimental results, a stable operating characteristics of 50 +3% duty ratio was obtained from the sinusoidal input wave of 370 mV.

• Journal of Power Electronics
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• v.14 no.1
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• pp.48-60
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• 2014

Multilevel inverters have been widely used for high-voltage and high-power applications. Their performance is greatly superior to that of conventional two-level inverters due to their reduced total harmonic distortion (THD), lower switch ratings, lower electromagnetic interference, and higher dc link voltages. However, they have some disadvantages such as an increased number of components, a complex pulse width modulation control method, and a voltage-balancing problem. In this paper, a novel nine-level reduced switch cascaded multilevel inverter based on a multilevel DC link (MLDCL) inverter topology with reduced switching components is proposed to improve the multilevel inverter performance by compensating the above mentioned disadvantages. This topology requires fewer components when compared to diode clamped, flying capacitor and cascaded inverters and it requires fewer carrier signals and gate drives. Therefore, the overall cost and circuit complexity are greatly reduced. This paper presents modulation methods by a novel reference and multicarrier based PWM schemes for reduced switch cascaded multilevel inverters (RSCMLI). It also compares the performance of the proposed scheme with that of conventional cascaded multilevel inverters (CCMLI). Simulation results from MATLAB/SIMULINK are presented to verify the performance of the nine-level RSCMLI. Finally, a prototype of the nine-level RSCMLI topology is built and tested to show the performance of the inverter through experimental results.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.49 no.9
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• pp.618-625
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• 2000

Recently PWM inverters are widely utilized for many industrial applications e.g. high performance motor drive and PWM techniques are newly developed for an accurate output voltage. Among them space voltage vector PWM(SVPWM) inverter has high voltage ratio and low harmonics compared to the conventional sinusoidal PWM inverter. However output voltage of PWM inverter is distorted and has error duet o the conducting voltage drop of switching devices and the dead time that is inevitable to prevent the shoot-through phenomenon. This paper investigates 3-phase SVPWM inverter which has a new compensation method against dead time and voltage drop. Proposed algorithm calculates gate pulse periods which directly compensates the dead time and nonlinear voltage drop without modification of reference voltages. Direct compensation of gate pulse periods produces exact output voltage and does not need additional circuits. The propose algorithm is verified through the simulation and experiments.

• JSTS:Journal of Semiconductor Technology and Science
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• v.3 no.2
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• pp.83-88
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• 2003

The reset operation of a CCD image sensor was improved using charge trapping of a MOS structure to realize a loe voltage driving. A DC bias generating circuit was added to the reset structure which sets reference voltage and holds the signal charge to be detected. The generated DC bias is added to the reset pulse to give an optimized voltage margin to the reset operation, and is controlled by adjustment of the threshold voltage of a MOS transistor in the circuit. By the pulse-type stress voltage applied to the gate, the electrons and holes were injected to the gate dielectrics, and the threshold voltage could be adjusted ranging from 0.2V to 5.5V, which is suitable for controlling the incomplete reset operation due to the process variation. The charges trapped in the silicon nitride lead to the positive and negative shift of the threshold voltage, and this phenomenon is explained by Poole-Frenkel conduction and Fowler-Nordheim conduction. A CCD image sensor with $492(H){\;}{\times}{\;}510(V)$ pixels adopting this structure showed complete reset operation with the driving voltage of 3.0V. The resolution chart taken with the image sensor shows no image flow to the illumination of 30 lux, even in the driving voltage of 3.0V.

• Journal of Power Electronics
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• v.16 no.2
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• pp.553-563
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• 2016

This paper presents a digital hardware implementation of a real-time simulator for a multiphase drive using a field-programmable gate array (FPGA) device. The simulator was developed with a modular and hierarchical design using very high-speed integrated circuit hardware description language (VHDL). Hence, this simulator is flexible and portable. A state-space representation model suitable for FPGA implementations was proposed for a dual three-phase induction machine (DTPIM). The simulator also models a two-level 12-pulse insulated-gate bipolar transistor (IGBT)-based voltage-source converter (VSC), a pulse-width modulation scheme, and a measurement system. Real-time simulation outputs (stator currents and rotor speed) were validated under steady-state and transient conditions using as reference an experimental test bench based on a DTPIM with 15 kW-rated power. The accuracy of the proposed digital hardware implementation was evaluated according to the simulation and experimental results. Finally, statistical performance parameters were provided to analyze the efficiency of the proposed DTPIM hardware implementation method.

• Proceedings of the IEEK Conference
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• 2001.06d
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• pp.151-154
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• 2001

In this Paper, a new harmonic imaging technique is proposed and evaluated experimentally. In the proposed method, a weighted chin signal with a hanning window is transmitted. The RF samples obtained on each array element are individually compressed by correlating with the reference signal defined as the 2nd harmonic (2f0) component of a transmitted chirp signal generated in a square-law system. The proposed method uses the compressed 2f0 component to form an image, for which the crosscorrelation term with f0 component should be suppressed below at least -60dB. After experiment, the 6dB pulse width and peak sidelobe level of the compressed 2f0 component were 0.7us and -60dB, respectively. This result shows that the proposed method can successfully eliminate the f0 component with a single transmit-receive event and therefore is more efficient than the conventional pulse inversion (PI) method in terms of frame rate. We also observed that the 2nd harmonic compont starts to decrease for source pressure higher than 210kPa in water, which implies that SNR of the 2nd harmonic imaging using short pulses cnanot be incresed beyond a certain limit.

• Journal of Power Electronics
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• v.16 no.6
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• pp.2045-2056
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• 2016

The input impedances of pulse width modulated (PWM) dc-to-dc converters, which dictate the outcomes of the dynamic interaction between dc-to-dc converters and their source subsystem, are analyzed in a general and unified manner. The input impedances of three basic PWM dc-to-dc converters are derived with both voltage mode control and current mode control. This paper presents the analytical expressions of the 24 input impedances of three basic PWM dc-to-dc converters with the two different control schemes in a factorized time-constant form. It also provides a comprehensive reference for future dynamic interaction analyses requiring knowledge of the converters' input impedances. The theoretical predictions of the paper are all supported by measurements on prototype dc-to-dc converters. The use of the presented results is demonstrated via a practical application example, which analyzes the small-signal dynamics of an input-filter coupled current-mode controlled buck converter. This elucidates the theoretical background for the previously-reported eccentric behavior of the converter.

• 전자공학회논문지 IE
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• v.47 no.3
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• pp.14-18
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• 2010

In this paper, we describe a CMOS DC-DC converter with a variable output voltage(5-7V @100mA) for a portable battery-operated system applications. The proposed DC-DC converter is used along with a Pulse-Frequency Modulation (PFM) method and consists of reference circuit, a feedback resistor, a controller, and an internal oscillator. The integrated DC-DC converter with two external passive components(L,C) has been designed and fabricated on a 0.5um 2-poly 3-metal CMOS process and could be applied to the Personal Digital Assistants(PDA), cellular Phone, Laptop Computer, etc.

• The Transactions of the Korean Institute of Power Electronics
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• v.3 no.1
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• pp.8-14
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• 1998

This paper describes a novel real-time based optimal Pulse Width Modulation (PWM) method suitable for microprocessor-based PWM inverters. Optimal switching patterns minimizing the performance index corresponding to the distortion between the reference and the controlled output voltages are decided by on-line calculation using the microprocessor-implemented control system. To show the effectiveness of the proposed PWM scheme, digital simulation studies and experiments using a 16-bit single-chip microcontroller (Intel 80C196KC) are performed. The results obtained from these simulation studies and experiments show that the proposed PWM scheme has better performance than the other methods such as the natural PWM and the direct PWM.