• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1571-1573
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• 1994

In order to substitute for the conventional measuring system which could bring about technical inconveiences, measuring techniques for the fast transient high voltage upto 100 kV and small signals less than 1 V are developed by use of Laser Source with Packets cell. for the former, capacitive voltage divider was specially designed for reducing the impulse voltage less than the half-wave voltage of pockets cell. For the tatter, interferometer type was employed as a mean to removing the fluctuation of Laser output intensity. And also the main beam through the Pockels cell and the reference beam from the Laser source are seperated before being detected respectively by photo diodes. And then, these two signals are amplified and compared for detecting only the small signals applied across the Pockels cell. Throughout this work, Laser-based measuring system is likely to enable us, at this moment, to detect correctly lightning impulse voltage upto 100 kV and the small signals less than 1 V upto the 2 MHz. Such a system could be employed as a possible diagnostic measuring system at the substation.

• Journal of Electrical Engineering and Technology
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• v.13 no.3
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• pp.1392-1397
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• 2018

The potentiometric measurement result for a high resistance up to $100P{\Omega}$ using a low resistance, a low voltage source and a commercial digital multimeter(DMM) is presented. With the method, a resistance can be easily, fast and economically measured. Using the method, resistance ranges over the $10G{\Omega}$ range which is difficult to measure using a commercial DMM and resistance ranges between $100T{\Omega}$ and $100P{\Omega}$ which cannot measure using an insulation tester were measured within accuracy of a few percent. It is expected that it can be useful to determine the temperature and voltage effect of a high resistance and an insulation material because it uses a reference resistance with a low resistance, very low temperature and voltage effect. Besides, it is expected that it can be useful to calibrate a dc high voltage divider with a large resistance ratio and a very low resistance because arbitrary resistance ratio measurements are possible with it.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.21-31
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• 2010

This paper presents a design of PLL and SSCG for reducing the EMI effect at the electronic machinery and tools for DisplayPort application. This system is composed of the essential element of PLL and Charge-Pump2 and Reference Clock Divider to implement the SSCG operation. In this paper, 270MHz/162MHz dual-mode PLL that can provide 10-phase and 1.35GHz/810MHz PLL that can reduce the jitter are designed for 2.7Gbps/162Gbps DisplayPort application. The jitter can be reduced drastically by combining 270MHz/162MHz PLL with 2-stage 5 to 1 serializer and 1.35GHz PLL with 2 to 1 serializer. This paper propose the frequency divider topology which can share the divider between modes and guarantee the 50% duty ratio. And, the output current mismatch can be reduced by using the proposed charge-pump topology. It is implemented using 0.13 um CMOS process and die areas of 270MHz/162MHz PLL and 1.35GHz/810MHz PLL are $650um\;{\times}\;500um$ and $600um\;{\times}\;500um$, respectively. The VCO tuning range of 270 MHz/162 MHz PLL is 330 MHz and the phase noise is -114 dBc/Hz at 1 MHz offset. The measured SSCG down spread amplitude is 0.5% and modulation frequency is 31kHz. The total power consumption is 48mW.

• Journal of Sensor Science and Technology
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• v.6 no.2
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• pp.137-144
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• 1997

In this paper, the design of a 10-bit 40-MS/s pipelined A/D converter is implemented to achieve low static power dissipation of 70 mW at the ${\pm}2.5\;V$ or +5 V power supply environment for high speed applications. A 1.5 b/stage pipeline architecture in the proposed ADC is used to allow large correction range for comparator offset and perform the fast interstage signal processing. According to necessity of high-performance op amps for design of the ADC, the new op amp with gain boosting based on a typical folded-cascode architecture is designed by using SAPICE that is an automatic design tool of op amps based on circuit simulation. A dynamic comparator with a capacitive reference voltage divider that consumes nearly no static power for this low power ADC was adopted. The ADC implemented using a $1.0{\mu}m$ n-well CMOS technology exhibits a DNL of ${\pm}0.6$ LSB, INL of +1/-0.75 LSB and SNDR of 56.3 dB for 9.97 MHz input while sampling at 40 MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.14 no.8
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• pp.777-786
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• 2003

The phase noise characteristics of the phase-locked loop frequency synthesizer were predicted based on the analysis for phase noise contribution of noise sources. The proposed phase noise model in this paper more accurately predicts the phase noise spectrum of frequency synthesizer. To accurately model the phase noise contribution of noise sources in frequency synthesizer, the phase noise sources were analyzed via modeling of the frequency divider and phase noise components using Leeson model for reference signal source and VCO. The phase noise transfer functions to VCO from noise sources were analyzed by superposition theory and linear operation of phase-locked loop. To evaluate the phase noise prediction model, the frequency synthesizers were fabricated and were evaluated by measured data and prediction data.